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ACT–E128K32 High Speed

4 Megabit EEPROM Multichip Module

Features

Package

■

Organized as 128K x 32

●

User

CIRCUIT TECHNOLOGY

www.aeroflex.com

■

4 Low Power 128K x 8 EEPROM Die in One MCM

■

Packaging – Hermetic Ceramic

Configurable to 256K x 16 or 512K x 8

■

CMOS and TTL Compatible Inputs and Outputs

■

Access Times of 120,140,150, 200, 250& 300ns

■

+5V ±10% Supply

■

Automatic Page Write Operation

■

Page Write Cycle Time: 10ms Max

■

Data Retention Ten Years Minimum

■

Low Power CMOS

■

Data Polling for End of Write Detection

■

Industry Standard Pinouts

66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,

Aeroflex code# "P3"

●

66 Pin, 1.08" x 1.08" x .185" PGA Type, With

Shoulder, Aeroflex code# "P7"

●

68 Lead, .88" x .88" x .200" Dual-Cavity Small

Outline Gull Wing, Aeroflex code# "F2"

(Drops into

the 68 Lead JEDEC .99"SQ CQFJ footprint)

●

■

MIL-PRF-38534 Compliant MCMs Available

■

Hardware and Software Data Protection

■

Internal Decoupling Capacitors for Low Noise

Operation

■

Commercial, Industrial and Military Temperature

Ranges

■

SMD# 5962–94585 Released (P7 & F2)

General Description

Block Diagram – PGA Type Package (P3,P7) & CQFP (F2)

The ACT–E128K32 is a high

speed, 4 megabit, CMOS

EEPROM multichip module

(MCM) designed for full

temperature range military,

space, or high reliability

applications. The MCM can be

organized as a 256K x 16 bits

or 512K x 8 bits device and is

input and output CMOS and

TTL compatible. Writing is

executed when the write enable

(WE) and chip enable (CE)

inputs are low and output

enable (OE) is high. Reading is

accomplished when WE is high

and CE and OE are both low.

Access

times

grades

120, 140, 150, 200, 250 & 300ns

are standard.

The

ACT–E128K32

packaged in a choice of

hermetically sealed co-fired

ceramic packages, a 66 pin,

1.08" sq PGA or a 68 lead, .88"

sq gullwing CQFP. The device

operates over the temperature

range of -55°C to +125°C and

military environment.

– A

128Kx8

I/O

0-7

I/O

8-15

I/O

24-31

Pin Description

I/O

0-31

Data I/O

0–16

Address Inputs

1-4

Write Enables

1-4

GND

Output Enable

Chip Enables

Power Supply

Ground

eroflex Circuit Technology - Advanced Multichip Modules © SCD1662 REV B 9/5/01

Absolute Maximum Ratings

Parameter

Operating Temperature

Storage Temperature Range

All Input Voltages with respect to Ground

All Output Voltages with respect to Ground

Voltage on OE and A9 with respect to Ground

Symbol

STG

Range

-55 to +125

-65 to +150

-0.6 to +6.25

-0.6 to V

+0.6

-0.6 to +13.5

Units

°C

NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Symbol

Parameter

Power Supply Voltage

Input High Voltage

Input Low Voltage

Case Operating Temperature (Military)

Minimum

+4.5

+2.0

-0.5

-55

Maximum

+5.5

+ 0.3

+0.8

+125

Units

°C

Capacitance

= 0V, f = 1MHz, T

= 25°C)

Symbol

(1-4)

Parameter

– A

Capacitance

Output Enable Capacitance

Write Enable Capacitance

Chip Enable Capacitance

I/O0 – I/O31 Capacitance

Maximum

Units

DC Characteristics

(Vcc = 5.0V, Vss = 0V, T

= -55°C to +125°C, unless otherwise specified)

Parameter

Input Leakage Current

Output Leakage Current

Operating Supply Current x 32 Mode

Operating Supply Current

Output Low Voltage

Output High Voltage

Sym

Conditions

= 5.5V, V

= GND to V

Minimum

Maximum

250

0.45

Units

µA

CE = OE = V

OUT

= GND to V

CE = V

OE = V

, f = 5Mhz

CE = V

, OE = V

f = 5Mhz

= +2.1mA, V

= 4.5V

= –400µA, V

= 4.5V

2.4

Truth Table

Mode

Standby

Read

Write

Out Disable

Write

Inhibit

Data I/O

High Z

Data Out

Data In

High Z

Aeroflex Circuit Technology

SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700

AC Write Characteristics

= 5V, V

= 0V, T

= -55°C to +125°C)

Parameter

Write Cycle Time

Address Set-up Time

Write Pulse Width (WE or CE)

Chip Enable Set-up Time

Address Hold Time

Data Hold Time

Chip Enable Hold Time

Data Set-up Time

Output Enable Set-up Time

Output Enable Hold Time

Symbol

CEH

OES

OEH

Min

150

100

Max

Units

AC Read Characteristics

= 5V, V

= 0V, T

= -55°C to +125°C)

Read Cycle Parameter

Read Cycle Time

Address Access Time

Chip Enable Access Time

Output Hold From Address Change,

OE or CE

Output Enable to Output Valid

Chip Enable or OE to High Z Output

Symbol

ACC

ACE

–120

Min

120

–140

140

–150

150

–200

200

–250

250

–300

Max

300

Max Min

Units

Page Write Characteristics

= 5V, V

= 0V, T

= -55°C to +125°C)

Parameter

Write Cycle Time

Address Set-up Time

Address Hold Time , See Note 1

Data Set-up Time

Data Hold Time

Write Pulse Width

Byte Load Cycle Time

Write Pulse Width High

Note 1 – Page Address must remain valid for duration of write cycle.

Symbol

BLC

WPH

Minimum

100

150

Maximum

Units

150

µs

Aeroflex Circuit Technology

SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700

Device Operation

The ACT-E128K32 is a high-performance

Electrically Erasable and Programmable

Read Only Memory. It is composed of four 1

megabit memory chips and is organized as

131,072 by 32 bits. The device offers access

times of 120 to 300ns with power dissipation

of 1.375W. When the device is deselected,

the CMOS standby current is less than 5 mA.

The ACT-E128K32 is accessed like a Static

RAM for the read or write cycle without the

need for external components. The device

contains a 128-byte page register to allow

writing of up to 128 bytes simultaneously.

During a write cycle, the address and 1 to

128 bytes of data are internally latched,

freeing the address and data bus for other

operations. Following the initiation of a write

cycle, the device will automatically write the

latched data using an internal control timer.

The end of a write cycle can be detected by

DATA polling of I/O7. Once the end of a write

cycle has been detected a new access for a

read or write can begin.

Aeroflex’s ACT-E128K32 has additional

features to ensure high quality and

manufacturability. The device utilizes internal

error correction for extended endurance and

improved data retention characteristics. An

optional software data protection mechanism

is available to guard against inadvertent

writes.

consists of setting the WE line low. The write

cycle begins when the last of either CE or

WE goes low.

The WE line transition from high to low also

initiates an internal delay timer to permit

page mode operation. Each subsequent WE

transition from high to low that occurs before

the completion of the

BLC

time out will restart

the timer from zero. The operation of the

timer is the same as a retriggable one-shot.

READ

The ACT-E128K32 stores data at the

memory location determined by the address

pins. When CE and OE are low and WE is

high, this data is present on the outputs.

When CE and OE are high, the outputs are in

a high impedance state. This two line control

prevents bus contention.

DATA POLLING

The ACT-E128K32 offers a data polling

feature which allows a faster method of

writing to the device. Figure 5 shows the

timing diagram for this function. During a

byte or page write cycle, an attempted read

of the last byte written will result in the

complement of the written data on I/O7 (For

each Chip). Once the write cycle has been

completed, true data is valid on all outputs

and the next cycle may begin. Data polling

may begin at any time during the write cycle.

WRITE

A write cycle is initiated when OE is high and

a low pulse is on WE or CE with CE or WE

low. The address is latched on the falling

edge of CE or WE whichever occurs last.

The data is latched by the rising edge of CE

or WE, whichever occurs first. A byte write

operation will automatically continue to

completion.

PAGE WRITE OPERATION

The ACT-E128K32 has a page write

operation that allows one to 128 bytes of data

to be written into the device and

consecutively loads during the internal

programming period. Successive bytes may

be loaded in the same manner after the first

data byte has been loaded. An internal timer

begins a time out operation at each write

cycle. If another write cycle is completed

within

BLC

or less, a new time out period

begins. Each write cycle restarts the delay

period. The write cycles can be continued as

long as the interval is less than the time out

period.

WRITE CYCLE TIMING

Figures 2 and 3 show the write cycle timing

relationships. A write cycle begins with

address application, write enable and chip

enable. Chip enable is accomplished by

placing the CE line low.

Write enable

Aeroflex Circuit Technology

SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700

The usual procedure is to increment the least

significant address lines from A0 through A6

at each write cycle. In this manner a page of

up to 128 bytes can be loaded in to the

EEPROM in a burst mode before beginning

the relatively long interval programming

cycle.

After the

BLC

time out is completed, the

EEPROM begins an internal write cycle.

During this cycle the entire page will be

written at the same time. The internal

programming cycle is the same regardless of

the number of bytes accessed.

byte write sequence of specific data to

specific locations. Power transitions will not

reset the software write protection.

Each 128K byte block of the EEPROM has

independent write protection. One or more

blocks may be enabled and the rest disabled

in any combination. The software write

protection guards against inadvertent writes

during power transitions, or unauthorized

modification using a PROM programmer.

HARDWARE DATA PROTECTION

These features protect against inadvertent

writes to the ACT-E128K32. These are

included to improve reliability during normal

operation:

A) Vcc Sense

While below 3.8V typical write cycles

are inhibited.

B) Write inhibiting

Holding OE low and either CE or WE

high inhibits write cycles.

C) Noise filter

Pulses of <10ns (TYP) on WE or CE

will not initiate a write cycle.

SOFTWARE DATA PROTECTION

A software write protection feature may be

enabled or disabled by the user. When

shipped by Aeroflex Microelectronics, the

ACT-E128K32 has the feature disabled.

Write access to the device is unrestricted.

To enable software write protection, the user

writes three access code bytes to three

special internal locations.

Once write

protection has been enabled, each write to

the EEPROM must use the same three byte

write sequence to permit writing. The write

protection feature can be disabled by a six

Aeroflex Circuit Technology

SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700