Table 1. 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ versions, V
DD
= 3 V to 5 V ± 10%, V
A
= V
DD
, V
B
= 0 V, −40°C < T
A
< +125°C,
unless otherwise noted.
Parameter
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity
2
Symbol
R-DNL
Conditions
R
WB
, V
A
= No Connect,
R
AB
= 10 kΩ, 50 kΩ, and 100
kΩ
R
WB
, V
A
= No Connect, R
AB
= 5
kΩ
R
WB
, V
A
= No Connect,
R
AB
= 10 kΩ, 50 kΩ, and 100 kΩ
R
WB
, V
A
= No Connect, R
AB
= 5
kΩ
Min
–0.5
Typ
1
±0.2
Max
+0.5
AD5171
Unit
LSB
–1
–1
–1.5
–30
±0.25
±0.25
±0.5
+1
+1
+1.5
+30
LSB
LSB
LSB
%
ppm/°C
Ω
Resistor Integral Nonlinearity
2
R-INL
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS POTENTIOMETER DIVIDER
MODE (Specifications apply to all RDACs)
Resolution
Differential Nonlinearity
4
Integral Nonlinearity
4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
∆R
AB
/R
AB
(∆R
AB
/R
AB
)/∆T
R
W
V
DD
= 5 V
35
60
115
N
DNL
INL
(∆V
W
/V
W
)/∆T
V
WFSE
V
WZSE
–0.5
–1
Code = 0x20
Code = 0x3F
Code = 0x00, R
AB
=10 kΩ,
50 kΩ, and 100 kΩ
Code = 0x00, R
AB
= 5 kΩ
With respect to GND
f = 1 MHz, measured to GND,
Code = 0x20
f = 1 MHz, measured to GND,
Code = 0x20
V
A
= V
B
= V
DD
/2
0.7 V
DD
–0.5
3.0
0
–1.5
0
0
±0.1
±0.2
5
-0.5
0.5
6
+0.5
+1
+0
1.5
2
V
DD
Bits
LSB
LSB
ppm/°C
LSB
LSB
LSB
V
pF
pF
nA
RESISTOR TERMINALS
Voltage Range
5
Capacitance
6
A, B
Capacitance
6
W
Common-Mode Leakage
DIGITAL INPUTS
Input Logic High (SDA and SCL)
Input Logic Low (SDA and SCL)
Input Logic High (AD0)
Input Logic Low (AD0)
Input Current
Input Capacitance
6
DIGITAL OUTPUTS
Output Logic Low (SDA)
Three-State Leakage Current (SDA)
Output Capacitance
6
POWER SUPPLIES
Power Supply Range
OTP Power Supply
7
Supply Current
OTP Supply Current
8
Power Dissipation
9
Power Supply Sensitivity
V
A, B, W
C
A, B
C
W
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
OL
I
OZ
C
OZ
V
DD
V
DD_OTP
I
DD
I
DD_OTP
P
DISS
PSSR
25
55
1
V
DD
+0.5
0.3V
DD
V
DD
1.0
±1
3
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
V
V
V
V
µA
pF
V
µA
pF
V
V
µA
mA
mW
%/%
I
OL
= 6 mA
V
IN
= 0 V or 5 V
3
2.7
6
4
100
−0.025
0.02
+0.001
0.4
±1
T
A
= 25°C
V
IH
= 5 V or V
IL
= 0 V
V
DD_OTP
= 6 V, T
A
= 25°C
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
5.5
6.5
8
0.04
+0.025
Rev. PrC | Page 3 of 20
AD5171
Parameter
DYNAMIC CHARACTERISTICS
6, 10, 11
Bandwidth –3 dB
Symbol
BW_5k
BW_10k
BW_50k
BW_100k
THD
t
S1
t
S_OTP
t
S2
e
N_WB
Conditions
Preliminary Technical Data
Min
Typ
1
1500
600
110
60
0.05
5
400
5
8
12
Max
Unit
kHz
kHz
kHz
kHz
%
µs
ms
µs
nV/√Hz
nV/√Hz
R
AB
= 5 kΩ, Code = 0x20
R
AB
= 10 kΩ, Code = 0x20
R
AB
= 50 kΩ, Code = 0x20
R
AB
= 100 kΩ, Code = 0x20
V
A
=1 V rms, R
AB
= 10 kΩ,
V
B
= 0 V D
C
, f = 1 kHz
V
A
= 5 V ± 1 LSB error band,
V
B
= 0, measured at V
W
V
A
= 5 V ± 1 LSB error band,
V
B
= 0, measured at V
W
V
A
= 5 V ±1 LSB error band,
V
B
= 0, measured at V
W
R
AB
= 5 kΩ, f = 1 kHz,
Code = 0x20
R
AB
= 10 kΩ, f = 1 kHz,
Code = 0x20
Total Harmonic Distortion
Adjustment Settling Time
OTP Settling Time
12
Power-up Settling Time—Post Fuses Blown
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS
(Applies to all parts
6,12
)
SCL Clock Frequency
t
BUF
Bus Free Time between Start and Stop
t
HD;STA
Hold Time (Repeated Start)
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Start Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL signals
t
SU;STO
Setup Time for Stop Condition
1
2
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
400
After this period, the first
clock pulse is generated
1.3
0.6
1.3
0.6
0.6
0.1
0.3
0.3
0.6
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
50
0.9
Typicals represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Different from operating power supply, power supply for OTP is used one-time only.
8
Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value result in the minimum overall power consumption.
11
All dynamic characteristics use V
DD
= 5 V.
12
Different from settling time after fuse is blown. The OTP settling time occurs once only.
t
8
t
9
t
6
SCL
t
2
t
3
t
8
SDA
t
4
t
9
t
5
t
7
t
10
P
S
P
Figure 3. Interface Timing Diagram
Rev. PrC | Page 4 of 20
03437-0-024
t
1
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
V
DD
to GND
V
A
, V
B
, V
W
to GND
Maximum Current
I
WB
, I
WA
Pulsed
I
WB
Continuous (R
WB
≤ 1 kΩ, A open)
1
I
WA
Continuous (R
WA
≤ 1 kΩ, B open)
1
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (T
J
max)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Thermal Resistance
2
θ
JA
1
AD5171
Rating
–0.3, +7 V
GND, V
DD
±20 mA
±5 mA
±5 mA
0 V, V
DD
–40°C to +125°C
150°C
–65°C to +150°C
300°C
215°C
220°C
230°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. V
DD
= 5 V.
2
Package Power Dissipation = (T
J
max – T
A
) / θ
JA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
