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AD5332_15

2.5 V to 5.5 V, 230 A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs

厂商名称：ADI(亚德诺半导体)

厂商官网：https://www.analog.com

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a
2.5 V to 5.5 V, 230 A, Parallel Interface
Dual Voltage-Output 8-/10-/12-Bit DACs
AD5332/AD5333/AD5342/AD5343*
GENERAL DESCRIPTION
FEATURES
AD5332: Dual 8-Bit DAC in 20-Lead TSSOP
AD5333: Dual 10-Bit DAC in 24-Lead TSSOP
AD5342: Dual 12-Bit DAC in 28-Lead TSSOP
AD5343: Dual 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 230 A @ 3 V, 300 A @ 5 V
via
PD
Pin
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–V
REF
or 0–2 V
REF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via
LDAC
Pin
Asynchronous
CLR
Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 230
µA
at 3 V, and feature a power-down pin,
PD
that further reduces the current to 80 nA. These devices incor-
porate an on-chip output buffer that can drive the output to
both supply rails, while the AD5333 and AD5342 allow a choice
of buffered or unbuffered reference input.
The AD5332/AD5333/AD5342/AD5343 have a parallel interface.
CS
selects the device and data is loaded into the input registers
on the rising edge of
WR.
The GAIN pin on the AD5333 and AD5342 allows the output
range to be set at 0 V to V
REF
or 0 V to 2
×
V
REF
.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the
LDAC
pin.
An asynchronous
CLR
input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5332/AD5333/AD5342/AD5343 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5332 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
V
REF
A
V
DD
POWER-ON
RESET
DB
7
.
.
.
DB
0
INTER-
FACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
AD5332
8-BIT
DAC
BUFFER
V
OUT
A
CS
WR
A0
BUFFER
V
OUT
B
CLR
LDAC
RESET
POWER-DOWN
LOGIC
V
REF
B
PD
GND
*Protected
by U.S. Patent Number 5,969,657
.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD5332/AD5333/AD5342/AD5343–SPECIFICATIONS
noted.)
(V = 2.5 V to 5.5 V, V = 2 V. R = 2 k to GND; C =200 pF to GND; all specifications T to T unless otherwise
DD
REF
L
L
MIN
MAX
Parameter
1
Min
B Version
2
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5332
Resolution
Relative Accuracy
Differential Nonlinearity
AD5333
Resolution
Relative Accuracy
Differential Nonlinearity
AD5342/AD5343
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
5
Upper Deadband
Offset Error Drift
6
Gain Error Drift
6
DC Power Supply Rejection Ratio
6
DC Crosstalk
6
DAC REFERENCE INPUT
6
V
REF
Input Range
V
REF
Input Impedance
8
±
0.15
±
0.02
10
±
0.5
±
0.05
12
±
2
±
0.2
±
0.4
±
0.15
10
10
–12
–5
–60
200
±
1
±
0.25
±
4
±
0.5
±
16
±
1
±
3
±
1
60
60
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
% of FSR
% of FSR
mV
mV
ppm of FSR/°C
ppm of FSR/°C
dB
µV
Guaranteed Monotonic By Design Over All Codes
Guaranteed Monotonic By Design Over All Codes
Guaranteed Monotonic By Design Over All Codes
Lower Deadband Exists Only if Offset Error Is Negative
V
DD
= 5 V. Upper Deadband Exists Only if V
REF =
V
DD
∆V
DD
=
±
10%
R
L
= 2 kΩ to GND, 2 kΩ to V
DD
; C
L
= 200 pF to GND;
Gain = 0
Buffered Reference (AD5333 and AD5342)
Unbuffered Reference
Buffered Reference (AD5333 and AD5342)
Unbuffered Reference. Gain = 1, Input Impedance = R
DAC
Unbuffered Reference. Gain = 2, Input Impedance = R
DAC
Frequency = 10 kHz
Frequency = 10 kHz (AD5332, AD5333, and AD5342)
Rail-to-Rail Operation
1
0.25
>10
180
90
–90
–90
V
DD
V
DD
Reference Feedthrough
Channel-to-Channel Isolation
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
4, 7
Maximum Output Voltage
4, 7
DC Output Impedance
Short Circuit Current
Power-Up Time
LOGIC INPUTS
6
Input Current
V
IL
, Input Low Voltage
V
V
MΩ
kΩ
kΩ
dB
dB
V min
V max
Ω
mA
mA
µs
µs
µA
V
V
V
V
V
V
pF
V
µA
µA
µA
µA
0.001
V
DD
– 0.001
0.5
25
16
2.5
5
±
1
0.8
0.6
0.5
2.4
2.1
2.0
3.5
2.5
300
230
5.5
450
350
V
DD
= 5 V
V
DD
= 3 V
Coming Out of Power-Down Mode. V
DD
= 5 V
Coming Out of Power-Down Mode. V
DD
= 3 V
V
IH
, Input High Voltage
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
V
DD
= 2.5 V
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
V
DD
= 2.5 V
Pin Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
All DACs active and excluding load currents
Unbuffered Reference. V
IH
= V
DD
, V
IL
= GND.
I
DD
increases by 50
µA
at V
REF
> V
DD
– 100 mV.
In Buffered Mode extra current is (5 +V
REF
/R
DAC
)
µA.
0.2
0.08
1
1
NOTES
1
See Terminology section.
2
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
3
Linearity is tested using a reduced code range: AD5332 (Code 8 to 255); AD5333 (Code 28 to 1023); AD5342/AD5343 (Code 115 to 4095).
4
DC specifications tested with outputs unloaded.
5
This corresponds to x codes. x = Deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF
= V
DD
and
“Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
–2–
REV. 0
AD5332/AD5333/AD5342/AD5343
AC CHARACTERISTICS
Parameter
2
Output Voltage Settling Time
AD5332
AD5333
AD5342
AD5343
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1
(V
DD
= 2.5 V to 5.5 V. R
L
= 2 k to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless
otherwise noted.)
B Version
3
Min
Typ
Max
6
7
8
8
0.7
6
0.5
3
0.5
3.5
200
–70
8
9
10
10
Unit
µs
µs
µs
µs
V/µs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Conditions/Comments
V
REF
= 2 V. See Figure 20
1/4 Scale to 3/4 Scale Change (40 H to C0 H)
1/4 Scale to 3/4 Scale Change (100 H to 300 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1 LSB Change Around Major Carry
V
REF
= 2 V
±
0.1 V p-p. Unbuffered Mode
V
REF
= 2.5 V
±
0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
Limit at T
MIN
, T
MAX
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
20
0
DD
= 2.5 V to 5.5 V, All specifications T
MIN
to T
MAX
unless otherwise noted.)
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Condition/Comments
CS
to
WR
Setup Time
CS
to
WR
Hold Time
WR
Pulsewidth
Data, GAIN, BUF, HBEN Setup Time
Data, GAIN, BUF, HBEN Hold Time
Synchronous Mode.
WR
Falling to
LDAC
Falling
Synchronous Mode.
LDAC
Falling to
WR
Rising
Synchronous Mode.
WR
Rising to
LDAC
Rising
Asynchronous Mode.
LDAC
Rising to
WR
Rising
Asynchronous Mode.
WR
Rising to
LDAC
Falling
LDAC
Pulsewidth
CLR
Pulsewidth
Time Between
WR
Cycles
A0 Setup Time
A0 Hold Time
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and
timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
Specifications subject to change without notice.
t
1
CS
t
2
t
3
t
13
t
4
t
5
WR
DATA,
GAIN,
BUF,
HBEN
LDAC
1
t
6
t
7
t
8
t
9
LDAC
2
CLR
A0
t
10
t
11
t
14
t
15
t
12
1
SYNCHRONOUS
LDAC
UPDATE MODE
2
ASYNCHRONOUS
LDAC
UPDATE MODE
Figure 1. Parallel Interface Timing Diagram
REV. 0
–3–
AD5332/AD5333/AD5342/AD5343
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (T
J
max – T
A
)/θ
JA
mW
θ
JA
Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W
θ
JA
Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
θ
JA
Thermal Impedance (28-Lead TSSOP) . . . . 97.9°C/W
θ
JC
Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W
θ
JC
Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
θ
JC
Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
AD5332BRU
AD5333BRU
AD5342BRU
AD5343BRU
Temperature Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
Package
Option
RU-20
RU-24
RU-28
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5332/AD5333/AD5342/AD5343 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD5332/AD5333/AD5342/AD5343
AD5332 FUNCTIONAL BLOCK DIAGRAM
V
REF
A
V
DD
AD5332 PIN CONFIGURATION
V
REF
B
1
POWER-ON
RESET
DB
7
.
.
.
DB
0
INTER-
FACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
V
OUT
B
INPUT
REGISTER
DAC
REGISTER
20
DB
7
19
DB
6
18
DB
5
AD5332
V
REF
A
2
V
OUT
A
3
V
OUT
B
4
8-BIT
17
DB
4
16
DB
3
8-BIT
DAC
BUFFER
V
OUT
A
GND
5
CS
6
AD5332
TOP VIEW
15
DB
2
(Not to Scale)
14
DB
1
7
WR
A0
8
CLR
9
LDAC
10
13
DB
0
12
V
DD
11
PD
CS
WR
A0
CLR
LDAC
RESET
POWER-DOWN
LOGIC
V
REF
B
PD
GND
AD5332 PIN FUNCTION DESCRIPTIONS
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13–20
Mnemonic
V
REF
B
V
REF
A
V
OUT
A
V
OUT
B
GND
CS
WR
A0
CLR
LDAC
PD
V
DD
DB
0
–DB
7
Function
Unbuffered reference input for DAC B.
Unbuffered reference input for DAC A.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active low Chip Select Input. This is used in conjunction with
WR
to write data to the parallel interface.
Active low Write Input. This is used in conjunction with
CS
to write data to the parallel interface.
Address pin for selecting which DAC A and DAC B.
Asynchronous active low control input that clears all input registers and DAC registers to zeros.
Active low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.
REV. 0
–5–
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参数对比
与AD5332_15相近的元器件有：AD5343_15、AD5333_15、AD5342_15。描述及对比如下：
型号 AD5332_15 AD5343_15 AD5333_15 AD5342_15
描述 2.5 V to 5.5 V, 230 A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs 2.5 V to 5.5 V, 230A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs 2.5 V to 5.5 V, 230A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs 2.5 V to 5.5 V, 230A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs
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器件捷径:
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ
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