a
FEATURES
256 Switches in a 16 16 Array
Wide Signal Range: to Supply Rails of 24 V or 12 V
Low On-Resistance: 200 Typ
TTL/CMOS/Microprocessor-Compatible Control Lines
Serial Input Simplifies Interface
Serial Output Allows Cascading for More Channels
Low Power Consumption: 2 mW Quiescent
Compact 44-Lead PLCC
X0
Y0
16
16 Crosspoint
Switch Array
AD75019
X15
V
DD
V
SS
V
CC
DGND
FUNCTIONAL BLOCK DIAGRAM
ANALOG
INPUTS/OUTPUTS
SERIAL DATA IN
SHIFT
REGISTER
CELL #256
+12V –12V
+5V DGND
LATCH
ANALOG
SWITCH
ANALOG
OUTPUTS/
INPUTS
AD75019
BUSED CLOCK
LINES
SERIAL
DATA
TO NEXT
STAGES
16 16 ARRAY OF SWITCHES,
LATCHES, AND SHIFT REGISTER
CELLS (ONLY TWO LOCATIONS
ARE SHOWN FOR CLARITY)
Y15
ANALOG
SWITCH
SERIAL
DATA
FROM
PRIOR
STAGES
BUSED CLOCK
LINES
SHIFT
REGISTER
CELL #1
LATCH
PARALLEL
CLOCK
SERIAL
CLOCK
PCLK
SCLK
SOUT
PRODUCT DESCRIPTION
The AD75019 contains 256 analog switches in a 16
×
16 array.
Any of the X or Y pins may serve as an input or output. Any or
all of the X terminals may be programmed to connect to any or
all of the Y terminals. The switches can accommodate signals
with amplitudes up to the supply rails and have a typical on-
resistance of 150
Ω.
Data is loaded serially via the SIN input and clocked into an on-
board 256-bit shift register via SCLK. When all the switch set-
tings have been programmed, data is transferred into a set of
256 latches via PCLK. The serial shift register is dynamic, so
there is a minimum clock rate of 20 kHz. The maximum clock
rate of 5 MHz allows loading times as short as 52
µs.
The switch
control latches are static and will hold their data as long as power
is applied.
To extend the number of switches in the array, you may cascade
multiple AD75019s. The SOUT output is the end of the shift
register, and may be connected to the SIN input of the next
AD75019.
The AD75019 is fabricated in Analog Devices’ BiMOS II
process. This epitaxial BiCMOS process features CMOS
devices for low distortion switches and bipolar devices for
ESD protection.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD75019–SPECIFICATIONS
(T = +25 C, V
A
1
DD
and V
SS
=
12 V, V
CC
= +5 V unless otherwise noted)
Min
V
SS
– 0.5
150
300
20
2
Typ
Max
V
DD
+ 0.5
300
500
30
10
25
Units
V
Ω
Ω
Ω
nA
pF
dB
dB
dB
0.01
20
4
8
5.5
0.8
±
1
±
1
10
%
MHz
ns
V
V
µA
µA
pF
AD75019
MULTIPLEXER
Input Signal Range
Switch ON Resistance, V
DD
and V
SS
=
±
12 V, V
SIGNAL
=
±
12 V
Switch ON Resistance, V
DD
and V
SS
=
±
5 V, V
SIGNAL
=
±
5 V
Switch ON Resistance Matching
2
, V
SIGNAL
=
±
12 V
Leakage Current, V
SIGNAL
=
±
10 V
Input/Output Capacitance
Isolation Between Any Two Channels
R
S
= 600
Ω,
R
L
= 10 kΩ, V
SIGNAL
= 2 V p-p
f
SIGNAL
= 1 kHz
f
SIGNAL
= 20 kHz
f
SIGNAL
= 1 MHz
Total Harmonic Distortion
R
S
= 600
Ω,
R
L
= 10 kΩ, V
SIGNAL
= 2 V p-p
Switch Frequency Response, –3 dB
R
S
= 600
Ω,
R
L
= 10 kΩ, V
SIGNAL
= 2 V p-p
Propagation Delay
DIGITAL INPUTS (SIN, SCLK, PCLK)
Logic Levels (TTL Compatible)
Input Voltage, Logic “1”
Input Voltage, Logic “0”
Input Current, V
IH
= 5.5 V
Input Current, V
IL
= 0.8 V
Input Capacitance
DIGITAL OUTPUTS (SOUT)
Logic Levels (TTL Compatible)
Output Voltage, Logic “1”
Output Voltage, Logic “0”
Output Current, V
OH
= 2.8 V
Output Current, V
OL
= 0.4 V
POWER SUPPLY REQUIREMENTS
Voltage Range, Total Analog
Voltage Range, Positive Analog
Voltage Range, Negative Analog
Voltage Range, Digital
Supply Current, SCLK = 5 MHz,
V
IL
= 0.8 V, V
IH
= 2.4 V
Supply Current, Quiescent,
V
IL
= 0.8 V, V
IH
= 2.4 V
TEMPERATURE RANGE
Operating
Storage
Symbol
V
IN
R
ON
R
ON
∆R
ON
C
IN
92
69
38
V
IH
V
IL
I
IH
I
IL
C
IN
2.4
0
V
OH
V
OL
I
OH
I
OL
V
DD
– V
SS
V
DD
– V
DGND
V
SS
– V
DGND
V
CC
– V
DGND
I
DD
, I
SS
I
CC
I
DD
, I
SS
I
CC
T
MIN
, T
MAX
2.8
0.4
3.2
3.2
9.0
(V
CC
– 0.5)
–20.7
4.5
25.2
25.2
0
5.5
±
70
800
400
100
+85
+150
V
V
mA
mA
V
V
V
V
mA
µA
µA
µA
°C
°C
5
_
_
–25
–65
NOTES
1
All minimum and maximum specifications are guaranteed, and specifications shown in
boldface
are tested on all production units at final electrical test. Results from those tests
are used to calculate outgoing quality levels.
2
Switch resistance matching is measured with zero volts at each analog input and refers to the difference between the maximum and minimum values.
Specifications subject to change without notice.
PIN FUNCTION DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
PCLK
SCLK
SIN
V
SS
NC
NC
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
X0
X1
X2
X3
X4
X5
X6
X7
Description
Parallel Clock Input
Serial Clock Input
Serial Data Input
Negative Analog Power Supply
No Internal Connection
No Internal Connection
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
X8
X9
X10
X11
X12
X13
X14
X15
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
NC
NC
V
DD
V
CC
DGND
SOUT
Description
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
No Internal Connection
No Internal Connection
Positive Analog Power Supply
Digital Power Supply
Digital Ground
Serial Data Output: Positive True
PIN CONFIGURATION
SOUT
DGND
SCLK
PCLK
V
CC
V
DD
NC
V
SS
SIN
NC
6
5
4
3
2
1
44 43 42 41 40
PIN 1
IDENTIFIER
NC
39
NC
38
Y7
37
Y6
36
Y5
35
Y4
34
Y3
33
Y2
32
Y1
31
Y0
30
X15
29
X14
Y15
7
Y14
8
Y13
9
Y12
10
Y11
11
Y10
12
Y9
13
Y8
14
X0
15
X1
16
X2
17
AD75019
TOP VIEW
(Not to Scale)
18 19 20 21 22 23 24 25 26 27 28
X11
X12
X4
X5
X3
X6
X7
X8
X9
X10
NC = NO CONNECT
X13
–2–
REV. C
AD75019
TIMING CHARACTERISTICS
1
(T = T
A
MIN
to T
MAX
, rated power supplies unless otherwise noted)
Symbol
t
1
t
2
t
3
t
4
t
5
(t
5
+ t
6
)
t
6
_
_
_
_
Value
20
100
40
100
65
5
65
70
52
20
1
Units
ns
ns
ns
ns
ns
ms
ns
ns
µs
kHz
µs
Condition
min
min
min
min
min
max
min
max
SCLK = 5 MHz
min
max
Parameter
Data Setup Time
SCLK Pulsewidth
Data Hold Time
SCLK Pulse Separation
SCLK to PCLK Delay
SCLK to PCLK Delay and Release
PCLK Pulsewidth
Propagation Delay, PCLK to Switches On or Off
Data Load Time
SCLK Frequency
SCLK, PCLK Rise and Fall Times
NOTES
1
Timing measurement reference level is 1.5 V.
Specifications subject to change without notice.
1
SCLK
0
TIMING DIAGRAM
t
4
LOAD DATA INTO
SERIAL REGISTER
DURING RISING EDGE
t
2
t
1
t
3
Y15–X15
1 = CLOSE
SIN
0 = OPEN
1
PCLK
0
Y15–X14
Y0–X0
t
5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
6
OPERATION TRUTH TABLE
Control Lines
PCLK
SCLK
1
1
0
0
1
X
SIN
X
Data
i
X
SOUT
X
Data
i-256
X
Operation/Comment
No operation.
The data on the SIN line is loaded into the serial register; data clocked into the
serial register 256 clocks ago appears at the SOUT output.
Data in the serial shift register transfers into the parallel latches which control the
switch array.
Power Supply Sequencing and Bypassing
APPLICATIONS INFORMATION
Loading Data
Data to control the switches is clocked serially into a 256-bit
shift register and then transferred in parallel to 256 bits of mem-
ory. The rising edge of SCLK, the serial clock input, loads data
into the shift register. The first bit loaded via SIN, the serial
data input, controls the switch at the intersection of row Y15
and column X15. The next bits control the remaining columns
(down to X0) of row Y15, and are followed by the bits for row
Y14, and so on down to the data for the switch at the intersec-
tion of row Y0 and column X0. The shift register is dynamic, so
there is a minimum clock rate, specified as 20 kHz.
After the shift register is filled with the new 256 bits of control
data, PCLK is activated (pulsed low) to transfer the data to the
parallel latches. Since the shift register is dynamic, there is a
maximum time delay specified before the data is lost: PCLK
must be activated and brought back high within 5 ms after fill-
ing the shift register. The switch control latches are static and
will hold their data as long as power is applied.
All junction-isolated parts operating on multiple power supplies
require proper attention to supply sequencing. Because BiMOS
II is a junction-isolated process, parasitic diodes exist between
V
DD
and V
CC
, and between V
SS
and DGND. As a result, V
DD
must always be greater than (V
CC
– 0.5 V), and V
SS
must always
be less than (DGND + 0.5 V).
If you can’t ensure that system power supplies will sequence to
meet these conditions, external Schottky (e.g., 1N5818) or
silicon (e.g., 1N4001) diodes may be used. To protect the posi-
tive side, the anode would connect to V
CC
(Pin 42) and the
cathode to V
DD
(Pin 41). For the negative side, connect the
anode to V
SS
(Pin 4) and the cathode to DGND (Pin 43).
Each of the three power supply pins [V
DD
(Pin 41), V
CC
(Pin
42) and V
SS
(Pin 4)] should be bypassed to DGND (Pin 43)
through a 0.1
µF
ceramic capacitor located close to the package
pins.
Transistor Count
AD75019 contains 5,472 transistors. This number may be used
To extend the number of switches in the array, you may cascade
for calculating projected reliability.
multiple AD75019s. The SOUT output is the end of the shift
register, and may be directly connected to the SIN input of the
next AD75019.
REV. C
–3–
AD75019
ABSOLUTE MAXIMUM RATINGS*
Min
V
DD
to DGND
V
SS
to DGND
V
CC
to DGND
V
DD
to V
SS
V
CC
to V
SS
Digital Inputs to DGND
Power Dissipation
Operating Temperature Range
Storage Temperature
Lead Temperature
–0.5
–25.2
–0.5
–0.5
–0.5
–0.3
0
–65
Max
+25.2
+0.5
+7.0
+25.2
+25.2
V
CC
+ 0.5
1.0
+70
+150
+300
Units
V
V
V
V
V
V
W
°C
°C
°C
Conditions
T
A
75°C
Soldering, 10 sec
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are Zener protected;
however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
AD75019JP
Temperature Range
0°C to +70°C
Package Option*
P-44A
*P = Plastic Leaded Chip Carrier (PLCC) Package.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Leaded Chip Carrier
(P-44A)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
6
7
PIN 1
IDENTIFIER
0.056 (1.42)
0.042 (1.07)
40
39
0.025 (0.63)
0.015 (0.38)
0.020
(0.50)
R
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.040 (1.01)
0.025 (0.64)
0.110 (2.79)
0.085 (2.16)
BOTTOM VIEW
(PINS UP)
17
18
29
28
0.020
(0.50)
R
0.656 (16.66)
SQ
0.650 (16.51)
0.695 (17.65)
SQ
0.685 (17.40)
–4–
REV. C
PRINTED IN U.S.A.
0.050
(1.27)
BSC
0.63 (16.00)
0.59 (14.99)
C1502c–0–8/99
