Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release.
2
Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise.
3
Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error.
4
Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise.
5
The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max.
Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the
Mode register. See the register description and circuit description for more details.
6
If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins,
and any additional capacitance connected to the MUXOUT. See the circuit description for more details.
7
For specified performance. Part is functional with Lower V
REF
8
Dynamic current charging the sigma-delta modulator input switching capacitor.
9
Outside the specified calibration range, calibration is possible but the performance may degrade.
10
These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
11
With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register).
12
External MCLKIN = 0 V or DV
DD
, Digital Inputs = 0 V or DV
DD
, P0 and P1 = 0 V or AV
DD
.
Specifications are subject to change without notice.
REV. 0
–3–
AD7738
TIMING SPECIFICATIONS
1, 2, 3
(AV
DD
= 5 V
Parameter
MASTER CLOCK RANGE
t
1
t
2
READ OPERATION
t
4
t
5 4
t
5A4, 5
t
6
t
7
t
8
t
9 6
WRITE OPERATION
t
11
t
12
t
13
t
14
t
15
t
16
0
0
50
50
0
10
0
30
25
50
50
0
60
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5%; DV
DD
= 2.7 V to 3.6 V or 5 V
Min
1
50
500
0
0
0
5%; Input Logic 0 = 0 V, Logic 1 = DV
DD
unless otherwise noted.)
Max
6.144
Unit
MHz
ns
ns
ns
60
80
ns
ns
Test Conditions/Comment
SYNC
Pulsewidth
RESET
Pulsewidth
CS
Falling Edge to SCLK Falling Edge Setup Time
SCLK Falling Edge to Data Valid Delay
DV
DD
of 4.75 V to 5.25 V
DV
DD
of 2.7 V to 3.3 V
CS
Falling Edge to Data Valid Delay
DV
DD
of 4.75 V to 5.25 V
DV
DD
of 2.7 V to 3.3 V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge after SCLK Rising Edge Hold Time
Bus Relinquish Time after SCLK Rising Edge
CS
Falling Edge to SCLK Falling Edge Setup
Data Valid to SCLK Rising Edge Setup Time
Data Valid after SCLK Rising Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge after SCLK Rising Edge Hold Time
Typ
80
NOTES
1
Sample tested during initial release to ensure compliance.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
3
See Figures 1 and 2.
4
These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
This specification is relevant only if CS goes low while SCLK is low.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.
The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing
characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications are subject to change without notice.
