is the center of the output voltage swing and can be V
DD
/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register.
Specifications subject to change without notice.
–2–
REV. A
AD7804/AD7805/AD7808/AD7809
AD7808/AD7809–SPECIFICATIONS
(AV
Reference = Internal Reference; C
L
= 100 pF; R
L
= 2 k
Parameter
STATIC PERFORMANCE
MAIN DAC
Resolution
Relative Accuracy
Gain Error
Bias Offset Error
2
Zero-Scale Error
Monotonicity
Minimum Load Resistance
SUB DAC
Resolution
Differential Nonlinearity
OUTPUT CHARACTERISTICS
Output Voltage Range
3
Voltage Output Settling Time to 10 Bits
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DC Output Impedance
Power Supply Rejection Ratio
DAC REFERENCE INPUTS
REF IN Range
REF IN Input Leakage
DIGITAL INPUTS
Input High Voltage, V
IH
@ V
DD
= 5 V
Input High Voltage, V
IH
@ V
DD
= 3.3 V
Input Low Voltage, V
IL
@ V
DD
= 5 V
Input Low Voltage, V
IL
@ V
DD
= 3.3 V
Input Leakage Current
Input Capacitance
Input Coding
REFERENCE OUTPUT
REF OUT Output Voltage
REF OUT Error
REF OUT Temperature Coefficient
REF OUT Output Impedance
POWER REQUIREMENTS
V
DD
(AV
DD
and DV
DD
)
I
DD
(AI
DD
Plus DI
DD
)
Normal Mode
System Standby (SSTBY) Mode
Power-Down (PD) Mode
@ +25°C
T
MIN
–T
MAX
Power Dissipation
Normal Mode
System Standby (SSTBY) Mode
Power-Down (PD) Mode
@ +25°C
T
MIN
–T
MAX
B Grade
1
10
±
4
±
3
±
60
±
35
9
2
8
±
0.125
±
0.5
V
BIAS
±
15/16
×
V
BIAS
V
BIAS
/16 to 31/16
×
V
BIAS
4
2.5
1
0.5
0.5
±
0.2
2
0.002
1.0 to V
DD
/2
±
1
2.4
2.1
0.8
0.6
±
10
8
Twos Comp/Binary
1.23
±
8
–100
5
3/5.5
18
250
1
3
99
1.38
5.5
16.5
and DV
DD
= 3.3 V 10% to 5 V 10%; AGND = DGND = 0 V;
to GND. Sub DAC at Midscale. All specifications T
MIN
to T
MAX
unless otherwise noted.)
DD
Units
Comments
Bits
LSB max
% FSR max
mV max
mV max
Bits
kΩ min
Bits
LSB typ
LSB max
V
V
µs
max
V/µs typ
nV-s typ
nV-s typ
nV-s typ
LSB typ
Ω
typ
%/% typ
V min to V max
µA
max
V min
V min
V max
V max
µA
max
pF max
DAC Code = 0.5 Full Scale
DAC Code = 000H for Offset Binary
and 200H for Twos Complement
Coding
Refers to an LSB of the Main DAC
Twos Complement Coding
Offset Binary Coding
Typically 1.5
µs
1 LSB Change Around the Major Carry
∆V
DD
±
10%
Typically
±
1 nA
V nom
% max
ppm/°C typ
kΩ nom
V min to V max
mA max
µA
max
µA
max
µA
max
mW max
mW max
µW
max
µW
max
Excluding Load Currents
V
IH
= V
DD
, V
IL
= DGND
V
IH
= V
DD
, V
IL
= DGND
V
IH
= V
DD
, V
IL
= DGND
Excluding Power Dissipated in Load
NOTES
1
Temperature range is – 40°C to +85°C.
2
Can be minimized using the Sub DAC.
3
V
BIAS
is the center of the output voltage swing and can be V
DD
/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register.
Specifications subject to change without notice.
REV. A
–3–
AD7804/AD7805/AD7808/AD7809
AD7804/AD7808 TIMING CHARACTERISTICS
1
(V
Internal Reference. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
6A
t
7
t
8
t
9
Limit at T
MIN
, T
MAX
All Versions
100
40
40
30
30
5
6
90
20
40
100
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
Description
CLKIN Cycle Time
CLKIN High Time
CLKIN Low Time
FSIN
Setup Time
Data Setup Time
Data Hold Time
LDAC
Hold Time
FSIN
Hold Time
LDAC, CLR
Pulsewidth
LDAC
Setup Time
DD
=
3.3 V
10% to 5 V
10%; AGND = DGND = 0 V; Reference =
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
t
1
CLKIN(I)
t
2
t
4
FSIN(I)
t
3
t
7
t
5
t
6
SDIN(I)
DB15
DB0
t
5
LDAC
1
t
6A
LDAC
2
t
9
t
8
CLR
t
8
1
TIMING REQUIREMENTS FOR SYNCHRONOUS
LDAC
UPDATE OR
LDAC
MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2
TIMING REQUIREMENTS FOR ASYNCHRONOUS
LDAC
UPDATE.
Figure 1. Timing Diagram for AD7804 and AD7808
–4–
REV. A
AD7804/AD7805/AD7808/AD7809
(V
DD
= 3.3 V
= Internal Reference. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
6A
t
7
t
8
t
9
t
10
t
11
t
12
Limit at T
MIN
, T
MAX
All Versions
25
4.5
25
4.5
25
4.5
6
40
0
40
100
40
100
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AD7805/AD7809 TIMING CHARACTERISTICS
1
10% to 5 V
10%; AGND = DGND = 0 V; Reference
Description
Mode Valid to Write Setup Time
Mode Valid to Write Hold Time
Address Valid to Write Setup Time
Address Valid to Write Hold Time
Data Setup Time
Data Hold Time
LDAC
Valid to Write Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulsewidth
Time Between Successive Writes
LDAC, CLR
Pulsewidth
Write to
LDAC
Setup Time
NOTE
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
t
1
MODE
t
2
t
3
A0, A1, A2
t
4
CS
t
7
t
8
t
10
t
9
WR
t
5
DATA
t
6
t
6A
LDAC
1
t
12
LDAC
2
t
11
t
11
CLR
1
TIMING REQUIREMENTS FOR SYNCHRONOUS
LDAC
UPDATE OR
LDAC
MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2
TIMING REQUIREMENTS FOR ASYNCHRONOUS
LDAC
UPDATE.
Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write
实时操作系统RTOS
