AD7823: 2.7 V to 5.5 V, 4.5 ms, 8-Bit ADC in 8-Lead
microSOIC/DIP Data Sheet
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REFERENCE MATERIALS
Technical Articles
•
MS-2210: Designing Power Supplies for High Speed ADC
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AD7823 Material Declaration
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PCN-PDN Information
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AD7823–SPECIFICATIONS
(GND = 0 V, V
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio
1, 2
Total Harmonic Distortion
1
Peak Harmonic or Spurious Noise
1
Intermodulation Distortion
2
2nd Order Terms
3rd Order Terms
DC ACCURACY
Resolution
Relative Accuracy
1
Differential Nonlinearity (DNL)
1
Gain Error
1
Offset Error
1
Total Unadjusted Error
1
Minimum Resolution for Which
No Missing Codes Are Guaranteed
ANALOG INPUT
Input Voltage Range
Input Leakage Current
2
Input Capacitance
2
REFERENCE INPUTS
2
V
REF
Input Voltage Range
Input Leakage Current
Input Capacitance
LOGIC INPUTS
2
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
Input Current, I
IN
Input Capacitance, C
IN
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
High Impedance Leakage Current
High Impedance Capacitance
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
1
POWER SUPPLY
V
DD
I
DD
Power Dissipation
Power-Down Mode
I
DD
Power Dissipation
Automatic Power Down
1 kSPS Throughput
10 kSPS Throughput
50 kSPS Throughput
Y Version
48
–70
–70
–77
–77
8
±
0.5
±
0.5
±
1
±
1
±
1
8
0
V
REF
±
1
15
1.2
V
DD
±
1
20
2.0
0.4
±
1
8
2.4
0.4
±
1
15
4
100
2.7–5.5
3.5
17.5
1
5
54
540
2.7
REF
= V
DD
. All specifications –40 C to +125 C unless otherwise noted.)
Unit
dB min
dB typ
dB typ
fa = 48 kHz, fb = 48.5 kHz
dB typ
dB typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
Bits
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
µs
typ
ns max
Volts
mA max
mW max
µA
max
µW
max
µW
max
µW
max
mW max
Test Conditions/Comments
f
IN
= 30 kHz, f
SAMPLE
= 133 kHz
Typically 10 nA, V
IN
= 0 V to V
DD
I
SOURCE
= 200
µA
I
SINK
= 200
µA
See DC Acquisition Section
For Specified Performance
Sampling at 133 kSPS and Logic
Inputs @ V
DD
or 0 V. V
DD
= 5 V
Nominal Supplies
Nominal Supplies
V
DD
= 3 V
NOTES
1
See Terminology.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
–2–
REV. C
AD7823
TIMING CHARACTERISTICS
1, 2
(–40 C to +125 C, unless otherwise noted)
Parameter
t
1
t
2
t
3
t
4
t
5 3
t
6 3
t
7 3
t
83, 4
t
POWERUP
V
DD
= 5 V
5
20
25
25
5
10
5
20
10
1.5
10%
V
DD
= 3 V
5
20
25
25
5
10
5
20
10
1.5
10%
Unit
µs
(max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (min)
µs
(max)
Conditions/Comments
Conversion Time Mode 1 Operation (High Speed Mode)
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
CONVST
Rising Edge to SCLK Rising Edge Set-Up Time
SCLK Rising Edge to D
OUT
Data Valid Delay
Data Hold Time after Rising Edge SCLK
Bus Relinquish Time after Falling Edge of SCLK
Power-Up Time
NOTES
1
Sample tested to ensure compliance.
2
See Figures 14, 15 and 16.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V
±
10% and
0.4 V or 2 V for V
DD
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics, t
8
, is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
