14-Output Clock Generator
AD9516-5
FEATURES
Low phase noise, phase-locked loop (PLL)
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
Six 1.6 GHz LVPECL outputs, arranged in 3 groups
Each group shares a 1-to-32 divider with coarse phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
Four 800 MHz LVDS outputs, arranged in 2 groups
Each group has 2 cascaded 1-to-32 dividers with coarse
phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in 64-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
CP
REFIN
REF2
CLK
CLK
DIVIDER
AND MUXes
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
∆t
∆t
∆t
∆t
PLL
REFIN
SWITCHOVER
AND MONITOR
REF1
STATUS
MONITOR
LVPECL
LVPECL
LVPECL
LVDS/CMOS
LVDS/CMOS
Figure 1.
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
The
AD9516-5
features six LVPECL outputs (in three pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide ratio
and coarse delay (or phase) to be set. The range of division for
the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow
a range of divisions up to a maximum of 1024.
The
AD9516-5
is available in a 64-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated by
connecting the charge pump supply (V
CP
) to 5.5 V. A separate
LVPECL power supply can be from 2.375 V to 3.6 V (nominal).
The
AD9516-5
is specified for operation over the industrial
range of −40°C to +85°C.
For applications requiring an integrated EEPROM, or needing
additional outputs, the
AD9520-5
and
AD9522-5
are available.
1
GENERAL DESCRIPTION
The
AD9516-5
1
provides a multi-output clock distribution function
with subpicosecond jitter performance, along with an on-chip PLL
that can be used with an external VCO/VCXO of up to 2.4 GHz.
The
AD9516-5
emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
AD9516
is used throughout the data sheet to refer to all members of the AD9516
family. However, when
AD9516-5
is used, it refers to that specific member of the
AD9516
family.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.
07972-001
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
AD9516-5
AD9516-5
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs ............................................................................... 6
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used) .............................................................. 7
Clock Output Absolute Time Jitter (Clock Generation
Using External VCXO) ................................................................ 8
Clock Output Additive Time Jitter (VCO Divider
Not Used)....................................................................................... 8
Clock Output Additive Time Jitter (VCO Divider Used) ....... 9
Delay Block Additive Time Jitter................................................ 9
Serial Control Port ..................................................................... 10
PD, RESET, and SYNC Pins ..................................................... 10
LD, STATUS, and REFMON Pins............................................ 11
Power Dissipation....................................................................... 11
Timing Characteristics .............................................................. 13
Absolute Maximum Ratings.......................................................... 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 23
Detailed Block Diagram ................................................................ 24
Theory of Operation ...................................................................... 25
Operational Configurations...................................................... 25
Lock Detect ................................................................................. 31
Clock Distribution ..................................................................... 35
Reset Modes ................................................................................ 43
Power-Down Modes .................................................................. 43
Serial Control Port ......................................................................... 44
Serial Control Port Pin Descriptions....................................... 44
General Operation of Serial Control Port............................... 44
Instruction Word (16 Bits)........................................................ 45
MSB/LSB First Transfers ........................................................... 45
Thermal Performance.................................................................... 48
Register Maps.................................................................................. 49
Register Map Overview ............................................................. 49
Register Map Descriptions........................................................ 52
Applications Information .............................................................. 71
Frequency Planning Using the AD9516 .................................. 71
Using the AD9516 Outputs for ADC Clock Applications .... 71
LVPECL Clock Distribution ..................................................... 72
LVDS Clock Distribution .......................................................... 72
CMOS Clock Distribution ........................................................ 73
Outline Dimensions ....................................................................... 74
Ordering Guide .......................................................................... 74
Rev. A | Page 2 of 76
AD9516-5
REVISION HISTORY
8/11—Rev. 0 to Rev. A
Changes to Features, Applications, and General Description ..... 1
Changes to CPRSET Pin Resistor Parameter, Table 1 .................. 4
Change to P = 2 DM (2/3) Parameter, Table 2 .............................. 5
Changes Test Conditions/Comments, Table 4 .............................. 6
Moved Table 5 to End of Specifications and Renumbered
Sequentially ...................................................................................... 13
Change to Shortest Delay Range Parameter,
Test Conditions/Comments, Table 14 .......................................... 13
Moved Timing Diagrams ............................................................... 14
Change to Endnote, Table 16 ......................................................... 15
Change to Caption, Figure 8 .......................................................... 18
Change to Captions, Figure 20 and Figure 21 ............................. 20
Moved Figure 23 and Figure 24 ..................................................... 21
Added Figure 31; Renumbered Sequentially ............................... 22
Change to Mode 1—Clock Distribution or External VCO <
1600 MHz Section ..........................................................................25
Changes to Mode 2 (High Frequency Clock Distribution)—
CLK or External VCO > 1600 MHz; Change to Table 22 .......... 26
Change to Charge Pump (CP) Section ......................................... 28
Changes to PLL Reference Inputs and Reference Switchover
Sections ............................................................................................. 29
Changes to Prescaler Section and Table 24 .................................. 30
Changes to A and B Counters, Digital Lock Detect (DLD),
and Current Source Digital Lock Detect (CSDLD) Sections .... 31
Change to Holdover Section .......................................................... 32
Changes to Automatic/Internal Holdover Mode ........................ 34
Changes to Clock Distribution Section........................................ 35
Changes to Channel Dividers—LVDS/CMOS Outputs
Section .............................................................................................. 37
Change to the Instruction Word (16 Bits) Section ..................... 45
Change to Figure 53 ........................................................................ 46
Changes to θ
JA
and Ψ
JT
Parameters, Table 46 ............................... 48
Changes to Register Address 0x003 and
Register Address 0x01C, Table 47 ................................................. 49
Changes to Register Address 0x003, Table 48 ............................. 52
Changes to Register Address 0x016, Bits[2:0], Table 49 ............ 54
Changes to Register Address 0x01C, Bits[4:3], Table 49 ........... 57
Changes to Register Address 0x191, Register Address 0x194,
and Register Address 0x197, Bit 5, Table 53 ................................ 66
Added Frequency Planning Using the AD9516 Section ............ 71
Changes to LVPECL Clock Distribution and LVDS Clock
Distribution Sections; Changes to Figure 59, Figure 60, and
Figure 61 ........................................................................................... 72
1/09—Revision 0: Initial Version
Rev. A | Page 3 of 76
AD9516-5
SPECIFICATIONS
Typical is given for V
S
= V
S_LVPECL
= 3.3 V ± 5%; V
S
≤ V
CP
≤ 5.25 V; T
A
= 25°C; R
SET
= 4.12 kΩ; CP
RSET
= 5.1 kΩ, unless otherwise noted.
Minimum and maximum values are given over full V
S
and T
A
(−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
V
S
V
S_LVPECL
V
CP
RSET Pin Resistor
CPRSET Pin Resistor
Min
3.135
2.375
V
S
2.7
Typ
3.3
Max
3.465
VS
5.25
10
Unit
V
V
V
kΩ
kΩ
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA
(CP_lsb = 600 μA); actual current can be calculated by:
CP_lsb = 3.06/CPRSET; connect to ground
4.12
5.1
PLL CHARACTERISTICS
Table 2.
Parameter
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
1.3
2.9
6.0
1.35
1.30
4.0
4.4
20
0
0.8
2.0
−100
2
100
45
0.8
+100
Min
Typ
Max
Unit
Test Conditions/Comments
Differential mode (can accommodate single-ended
input by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match V
CM
(self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew
rate; see Figure 13
Self-bias voltage of REFIN
1
Self-bias voltage of REFIN
1
Self-biased
1
Self-biased
1
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/μs
Slew rate > 50 V/μs; CMOS levels
Should not exceed V
S
p-p
0
250
1.60
1.50
4.8
5.3
250
MHz
mV p-p
1.75
1.60
5.9
6.4
250
250
V
V
kΩ
kΩ
MHz
MHz
V p-p
V
V
μA
pF
MHz
MHz
ns
ns
ns
Each pin, REFIN/REFIN (REF1/REF2)
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
Programmable
With CP
RSET
= 5.1 kΩ
CP
V
= V
CP
/2
CHARGE PUMP (CP)
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
I
CP
High Impedance Mode Leakage
Sink-and-Source Current Matching
I
CP
vs. CP
V
I
CP
vs. Temperature
4.8
0.60
2.5
2.7/10
1
2
1.5
2
mA
mA
%
kΩ
nA
%
%
%
Rev. A | Page 4 of 76
0.5 < CP
V
< V
CP
− 0.5 V
0.5 < CP
V
< V
CP
− 0.5 V
V
CP
= VCP/2 V
AD9516-5
Parameter
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
Min
Typ
Max
Unit
Test Conditions/Comments
See the VCXO/VCO Feedback Divider N—P, A, B section
300
600
900
200
1000
2400
3000
3000
300
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
A, B counter input frequency (prescaler input frequency
divided by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 49
Off
330
440
550
660
770
880
990
ps
ps
ps
ps
ps
ps
ps
ps
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the
value of the N divider)
−165
−162
−151
−143
−220
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL DIGITAL LOCK DETECT WINDOW
2
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
To Unlock After Lock (Hysteresis)
2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
1
2
3.5
7.5
3.5
7
15
11
ns
ns
ns
ns
ns
ns
Reference slew rate > 0.25 V/ns; FOM + 10 log(f
PFD
) is
an approximation of the PFD/CP in-band phase noise
(in the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N)
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. A | Page 5 of 76
模拟与混合信号
