14-Bit, 160 MSPS, 2×/4×/8× Interpolating
Dual TxDAC+
®
Digital-to-Analog Converter
AD9775
FEATURES
14-bit resolution, 160 MSPS/400 MSPS input/output
data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
f
S
/4, f
S
/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Excellent ac performance
SFDR: −71 dBc @ 2 MHz to 35 MHz
W-CDMA ACPR: −71 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or TTL/CMOS/LVPECL
compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: 1.2 W @ 3.3 V typical
On-chip, 1.2 V reference
80-lead, thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
FUNCTIONAL BLOCK DIAGRAM
IDAC
AD9775
HALF-
BAND
FILTER1*
16
16
HALF-
BAND
FILTER2*
16
HALF-
BAND
FILTER3*
COS
GAIN
DAC
SIN
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
OFFSET
DAC
DATA
ASSEMBLER
14
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
14
I
LATCH
f
DAC
/2, 4, 8
SIN
Q
LATCH
16
16
16
16
WRITE
SELECT
MUX
CONTROL
CLOCK OUT
FILTER
BYPASS
MUX
/2
(
f
DAC
)
/2
/2
/2
COS
IDAC
I
OUT
SPI INTERFACE AND
CONTROL REGISTERS
PRESCALER
VREF
16
I/Q DAC
GAIN/OFFSET
REGISTERS
DIFFERENTIAL
CLK
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
02858-001
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
PHASE DETECTOR
AND VCO
IOFFSET
AD9775
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Product Highlights ....................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Dynamic Specifications ............................................................... 6
Digital Specifications ................................................................... 7
Digital Filter Specifications ......................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Thermal Resistance ...................................................................... 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 17
Mode Control (via SPI Port) ......................................................... 18
Register Descriptions ..................................................................... 19
Address 0x00 ............................................................................... 19
Address 0x01 ............................................................................... 19
Address 0x02 ............................................................................... 19
Address 0x03 ............................................................................... 20
Address 0x04 ............................................................................... 20
Address 0x05, Address 0x09 ..................................................... 20
Address 0x06, Address 0x0A..................................................... 20
Address 0x07, Address 0x0B ..................................................... 20
Address 0x08, Address 0x0C..................................................... 20
Address 0x08, Address 0x0C..................................................... 20
Functional Description .................................................................. 21
Serial Interface for Register Control ........................................ 21
General Operation of the Serial Interface ............................... 21
Instruction Byte .......................................................................... 22
Serial Interface Port Pin Descriptions ..................................... 22
MSB/LSB Transfers..................................................................... 22
Notes on Serial Port Operation ................................................ 22
DAC Operation........................................................................... 24
1R/2R Mode ................................................................................ 25
Clock Input Configurations...................................................... 25
Programmable PLL .................................................................... 26
Power Dissipation....................................................................... 27
Sleep/Power-Down Modes........................................................ 28
Two-Port Data Input Mode ...................................................... 28
PLL Enabled, Two-Port Mode .................................................. 28
DATACLK Inversion.................................................................. 29
DATACLK Driver Strength....................................................... 29
PLL Enabled, One-Port Mode .................................................. 29
ONEPORTCLK Inversion......................................................... 29
ONEPORTCLK Driver Strength.............................................. 30
IQ Pairing .................................................................................... 30
PLL Disabled, Two-Port Mode................................................. 30
PLL Disabled, One-Port Mode ................................................. 30
Digital Filter Modes ................................................................... 31
Amplitude Modulation.............................................................. 31
Modulation, No Interpolation .................................................. 32
Modulation, Interpolation = 2× ............................................... 33
Modulation, Interpolation = 4× ............................................... 34
Modulation, Interpolation = 8× ............................................... 35
Zero Stuffing ............................................................................... 36
Interpolating (Complex Mix Mode)........................................ 36
Operations on Complex Signals............................................... 36
Complex Modulation and Image Rejection of Baseband
Signals .......................................................................................... 37
Image Rejection and Sideband Suppression of Modulated
Carriers ........................................................................................ 38
Applying the Output Configurations........................................... 42
Unbuffered Differential Output, Equivalent Circuit ............. 42
Differential Coupling Using a Transformer............................ 42
Differential Coupling Using an Op Amp................................ 43
Interfacing the AD9775 with the AD8345 Quadrature
Modulator.................................................................................... 43
Evaluation Board ............................................................................ 44
Outline Dimensions ....................................................................... 54
Ordering Guide .......................................................................... 54
Rev. E | Page 2 of 56
AD9775
REVISION HISTORY
12/06—Rev. D to Rev. E
Changes to Figure 52, Figure 54, Figure 55, and Figure 56 .......29
1/06—Rev. C to Rev. D
Updated Formatting..........................................................Universal
Changes to Figure 32 .................................................................... 22
Changes to Figure 108 .................................................................. 55
Updated Outline Dimensions...................................................... 58
Changes to Ordering Guide......................................................... 58
6/04—Rev. B to Rev. C
Updated Layout .................................................................Universal
Changes to DC Specifications ....................................................... 5
Changes to Absolute Maximum Ratings...................................... 9
Changes to the DAC Operation Section .................................... 25
Inserted Figure 38.......................................................................... 25
Changes to Figure 40 .................................................................... 26
Changes to Table 11 ...................................................................... 28
Changes to Programmable PLL Section..................................... 28
Changes to Figures 49, 50, and 51............................................... 29
Changes to the PLL Enabled, One-Port Mode Section............ 30
Changes to the PLL Disabled, One-Port Mode Section........... 31
Changes to the Ordering Guide .................................................. 57
Updated Outline Dimensions...................................................... 57
3/03—Rev. A to Rev. B
Changes to Register Description—Address 04h ....................... 16
Changes to Equation 1.................................................................. 16
Changes to Figure 8....................................................................... 20
2/03—Rev. 0 to Rev. A
Edits to Features ...............................................................................1
Edits to DC Specifications ..............................................................3
Edits to Dynamic Specifications ....................................................4
Edits to Pin Function Descriptions ...............................................8
Edits to Table I ............................................................................... 14
Edits to Register Description—Address 02h ............................. 15
Edits to Register Description—Address 03h ............................. 16
Edits to Register Description—Address 07h, 0Bh.................... 16
Edits to Equation 1........................................................................ 16
Edits to MSB/LSB Transfers......................................................... 18
Edits to Programmable PLL......................................................... 21
Added New Figure 14 ................................................................... 22
Renumbered Figures 15–69 ......................................................... 22
Added Two-Port Data Input Mode Section............................... 23
Edits to PLL Enabled, Two-Port Mode ...................................... 24
Edits to Figure 19 .......................................................................... 24
Edits to Figure 21 .......................................................................... 25
Edits to PLL Disabled, Two-Port Mode ..................................... 25
Edits to Figure 22 .......................................................................... 25
Edits to Figure 23 .......................................................................... 26
Edits to Figure 26a ........................................................................ 27
Edits to Complex Modulation and Image Rejection of Baseband
Signals ............................................................................................. 31
Edits to Evaluation Board ............................................................ 39
Edits to Figures 56–59 .................................................................. 40
Replaced Figures 60–69................................................................ 42
Updated Outline Dimensions...................................................... 49
Rev. E | Page 3 of 56
AD9775
GENERAL DESCRIPTION
The AD9775
1
is the 14-bit member of the AD977x pin-
compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family. The AD977x family features a
serial port interface (SPI) that provides a high level of
programmability, thus allowing for enhanced system-level
options. These options include selectable 2×/4×/8×
interpolation filters; f
S
/2, f
S
/4, or f
S
/8 digital quadrature
modulation with image rejection; a direct IF mode;
programmable channel gain and offset control; programmable
internal clock divider; straight binary or twos complement data
interface; and a single-port or dual-port data interface.
The selectable 2×/4×/8× interpolation filters simplify the
requirements of the reconstruction filters while simultaneously
enhancing the pass-band noise/distortion performance of
TxDAC+ devices. The independent channel gain and offset
adjust registers allow the user to calibrate LO feedthrough and
sideband suppression errors associated with analog quadrature
modulators. The 6 dB of gain adjustment range can also be used
to control the output power level of each DAC.
The AD9775 can perform f
S
/2, f
S
/4, and f
S
/8 digital modulation
and image rejection when combined with an analog quadrature
modulator. In this mode, the AD9775 accepts I and Q complex
data (representing a single or multicarrier waveform), generates
a quadrature modulated IF signal along with its orthogonal
representation via its dual DACs, and presents these two
reconstructed orthogonal IF carriers to an analog quadrature
modulator to complete the image rejection upconversion
process. Another digital modulation mode (that is, the direct IF
mode) allows the original baseband signal representation to be
frequency translated such that pairs of images fall at multiples
of one-half the DAC update rate.
The AD977x family includes a flexible clock interface that
accepts differential or single-ended sine wave or digital logic
inputs. An internal PLL clock multiplier is included and
generates the necessary on-chip high frequency clocks. It can
also be disabled to allow the use of a higher performance
external clock source. An internal programmable divider
simplifies clock generation in the converter when using an
external clock source. A flexible data input interface allows for
straight binary or twos complement formats and supports
single-port interleaved or dual-port data.
Dual high performance DAC outputs provide a differential
current output programmable over a 2 mA to 20 mA range.
The AD9775 is manufactured on an advanced 0.35 micron
CMOS process, operates from a single supply of 3.1 V to 3.5 V,
and consumes 1.2 W of power.
Targeted at wide dynamic range, multicarrier and multistandard
systems, the superb baseband performance of the AD9775 is
ideal for wideband CDMA, multicarrier CDMA, multicarrier
TDMA, multicarrier GSM, and high performance systems
employing high order QAM modulation schemes. The image
rejection feature simplifies and can help reduce the number of
signal band filters needed in a transmit signal chain. The direct
IF mode helps to eliminate a costly mixer stage for a variety of
communications systems.
PRODUCT HIGHLIGHTS
1.
The AD9775 is the 14-bit member of the AD977x pin-
compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family.
Direct IF transmission capability for 70 MHz + IFs through
a novel digital mixing process.
f
S
/2, f
S
/4, and f
S
/8 digital quadrature modulation and user-
selectable image rejection to simplify/remove cascaded
SAW filter stages.
A 2×/4×/8× user-selectable, interpolating filter eases data
rate and output signal reconstruction filter requirements.
User-selectable, twos complement/straight binary data
coding.
User-programmable, channel gain control over 1 dB range
in 0.01 dB increments.
User programmable channel offset control ±10% over the
FSR.
Ultrahigh speed 400 MSPS DAC conversion rate.
Internal clock divider provides data rate clock for easy
interfacing.
Flexible clock input with single-ended or differential input,
CMOS, or 1 V p-p LO sine wave input capability.
Low power: complete CMOS DAC operates on 1.2 W from
a 3.1 V to 3.5 V single supply. The 20 mA full-scale current
can be reduced for lower power operation and several sleep
functions are provided to reduce power during idle
periods.
On-chip voltage reference. The AD9775 includes a 1.20 V
temperature compensated band gap voltage reference.
80-lead, thin quad flat package, exposed pad (TQFP_EP).
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
1
Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other patents pending.
Rev. E | Page 4 of 56
AD9775
SPECIFICATIONS
DC SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC Accuracy
1
Integral Nonlinearity
Differential Nonlinearity
ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)
Offset Error
Gain Error (with Internal Reference)
Gain Matching
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
Gain, Offset Cal DACs, Monotonicity Guaranteed
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (with Internal Reference)
Reference Voltage Drift
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (I
AVDD
)
4
I
AVDD
in SLEEP Mode
CLKVDD
Voltage Range
Clock Supply Current (I
CLKVDD
)
4
CLKVDD (PLL ON)
Clock Supply Current (I
CLKVDD
)
DVDD
Voltage Range
Digital Supply Current (I
DVDD
)
4
Nominal Power Dissipation
P
DIS 5
P
DIS
IN PWDN
Power Supply Rejection Ratio—AVDD
OPERATING RANGE
1
2
Min
14
−5
−3
−0.02
−1.0
−1.0
2
−1.0
Typ
Max
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
±1.5
±1.0
±0.01
±0.1
+5
+3
+0.02
+1.0
+1.0
20
+1.25
200
3
1.14
1.20
100
1.26
V
nA
V
kΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
0.1
7
0.5
0
50
±50
1.25
3.1
3.3
72.5
23.3
3.3
8.5
23.5
3.5
76
26
3.5
10.0
V
mA
mA
V
mA
mA
3.1
3.1
3.3
34
380
1.75
6.0
±0.4
3.5
41
410
−40
+85
V
mA
mW
W
mW
% of FSR/V
°C
Measured at I
OUTA
driving a virtual ground.
Nominal full-scale current, I
OUTFS
, is 32 × the I
REF
current.
3
Use an external amplifier to drive any external load.
4
100 MSPS f
DAC
with f
OUT
= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.
5
400 MSPS f
DAC
= 50 MSPS, f
S
/2 modulation, PLL enabled.
Rev. E | Page 5 of 56
