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ANALOG

DEVICES

TECHNICAL

DATA

LowCostGeneral urpose

Analog-

To-Digital onverter

---1

PRELIMINARY

OBS

FEATURES

12 Bit Resolution and Accuracy

Very High Performance/Cost Ratio

Monotonic from OoCto +50°C

40J,Ls

Conversion Time

Low Profile Module

Parallel and Serial Outputs

TTL/DTL Logic Levels

User Selected Input Ranges

Input Buffer Option Available

"""

GENERAL DESCRIPTION

The ADC-12QZ is a 12-bit successive approximation type

general purpose analog-to-digital converter that offers mod-

erate speed and good performance at very low cost. Analog

Devices' proprietary monolithic quad switches and a unique

combination of thin film and hybrid technology have been

incorporated in the ADC-12QZ, resulting in a converter that

has the basic performance of a much higher priced unit. It

is monotonic (no missing codes) from OoCto +50°C, and has

a maximum error of :tVzLSBrelative to full scale. The ADC-

12QZ is packaged in a convenient, small, low profile module,

and all of its logic inputs and outputs are fully TTL/DTL

compatible.

OLE

-~--

Cg~~ER:..n

STATUS

CLOCK

STROBE

BIT 1

IMSBI

BIT 2

PREVIOUS WORD, 0011

.. 0

NEW WORD.

010111101000

EASY TO USE

The ADC-12QZ was designed specifically to make it easy to

use. It contains its own temperature-compensated precision

voltage reference, and any of four input ranges (0 to +10V,

:tl0V, 0 to +5V, :t5V) can be selected with jumpers and con-

nections at the module terminals. If a high input impedance is

required, the ADC-12QZ can be special ordered with an in-

put buffer.

Binary output coding is used for unipolar operation, but for

operation in the bipolar mode, the parallel output data can be

either two's complement or offset binary at the user's option.

The two codes differ only in that the MSB output (pin 72) is

used for offset binary coding, while its complement, MSB (pin

70) is used for two's complement coding. STATUS, which in-

dicates when the parallel output data is valid, and its comple-

ment, STATUS, are both available.

A latched serial output having a nonreturn-to-zero (NRZ) for-

mat is taken from the output of a TTL flip-flop. The serial

data is transmitted MSB first in binary code for unipolar

r-'

Information furnished by Analog Devices is believed to be accurate

and reliable. However, no responsibility is assumed by Analog Devices

for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implica-

tion or otherwise under any patent or patent rights of Analog Devices.

operation and in offset binary code for bipolar operation. The

STROBE output is used to synchronize the serial data with a

receiving shift register.

TIMING

As shown in Figure 1, the leading edge ("0" to "1" transition)

of the convert command pulse sets the STATUS and MSB out-

puts to the "1" state, and the outputs of bits 2-12 to "0". The

conversion program begins on the trailing edge of the convert

command pulse with the starting of the internal clock. The bit

decisions are made on successive "1" to "0" clock pulse transi-

tions, with the MSB decision occurring first. The 200ns wide

strobe pulses are used to synchronize the transmission of serial

data. Serial data bits are valid on successive leading edges ("0"

to "1" transitions) of the strobe pulses. At the completion of

the conversion, the STATUS output returns to zero, signaling

that the parallel output data is valid.

..J

BIT 3

BIT 4

BIT 12

ILSBI

SERIAL

OUT

L...Jr1LJ',

Figure

ADC-12QZ

:-+--t

,',

'---'

Timing Diagram

Route 1 Industrial Park; P.O. Box 280; Norwood, Mass.02062

Tel: 617/329-4700

TWX:710/394-6577

HIGH PERFORMANCEENERAL

PURPOSE

AID CONVERTERS

ADC-QM, ADC-QU

GENERAL DESCRIPTION

These converters are characterized primarily by hig!!

performance and general utility. The use of J..I.DAdB>

mono-

lithic quad switches with J..I.DAC

monolithic thin film

resistance networks provide these converters with the best

stability and linearity generally available. Prices are kept at

moderate levels by large volume manufactUring.

OBS

BWCK DIAGRAM

ADC-QM & ADC-QU

3OK

lOOK ~

GAIN

ADC-QM

The ADC-QM is a high performance, general purpose

AID

con-

verter packaged in a low profile 2" x 4" module. It offers ex-

cellent stability over both time and temperature at moderate

cost. It is complete with an input buffer, and the desired input

range is selected by the user with jumpers and connections at

.the module terminals. The digital output code of the binary

version is natural binary for a unipolar input, but is selected by

the user to be either offset binary or two's complement with a

bipolar input. The ADC-QM is available in 8, 10, and 12

bit versions.

-15

OLE

ADC

ADC-12QM

ADC-12QU

SHA

SHA-IA

SHA-2A

SHA-IA

SHA-2A

34kHz

39kHz

50kHz

67kHz

ORDERING GUIDE: ADC-QM and ADC-QU

ADC-XX

/XXX

No. of

Bits

"'8

ADC-QU

The ADC-QU is a modular analog-to-digital converter that is

very similar to the ADC-QM, except that it offers an appre-

ciably shorter conversion time. The 12 bit version performs a

conversion in 15J..1.S

maximum. The ADC-QU's speed is the re-

sult of the use of Analog Devices' AD55 1

J..I.DAC8>

speed

high

quad current switches in its internal DAc. The ADC-QU is

pin-compatible with the ADC-QM, and in most applications

can serve as a direct plug-in replacement for it. When mounted

on an AC445 1 mounting card, the ADC-QU becomes a pin-

compatible substitute for the older model ADC-U.

DATA ACQUISITION APPLICATIONS

An ADC-QM or an ADC-QU can be combined with a SHA-IA

or SHA-2A sample-and-hold amplifier, and one or more MPX-

8A multiplexers to form a data acquisition subsystem. The

table below shows the maximum throughput rates (conversions!

sec) that can be achieved using various combinations of these

products. The settling time of the MPX-8A does not affect the

throughput rate because it can be settling on a new input signal

at the same time the

AID

converter is converting the signal

being held constant by the sample-and-hold amplifier.

MAX. THROUGHPUT RATE

',5V

3MEG

lOOK ~

ZERO

-15

.15V

211 0.-

00i't

GRO

3O~

Series

Output

Code

)61 r.

BIN (binary)

BCD (binary)

coded decimal)

Note: In the ADC-8QM and ADC-8QU, bit 8 is the LSB,

and pins 48,50,52 and 54 are deleted. In the ADC-I0QM

and ADC-IOQU, bit 10 is the LSB, and pins 48 and 50

are deleted.

CONVERTERS

SPECIFICATION

Model

Resolution,

Linearity

Bits

Error

SUMMARY

(Typical @ +25°C unless otherwise

ADC-QM

S, 10, 12

:t1f2LSB

U.5,

:t5, :tlO,

+10,+5

noted)

ADC-QU

Analog Input

Ranges! (Volts)

Input Impedance

Without Buffer2

With Buffer

Conversion Time

Digital Control

Inputs & Outputs

Data Outputs

Outpu t Codes

Standard

2.5k - 10k ohms

108 ohms

lSps

22ps

25ps

6.4ps

Bps

15ps

TTL/DTL Compatible

TTL Positive True

BIN, OBN, 2SC

BCD

"1" During Conversion

5ppm/C

50PV/C

75pV/C

+15V @ 25mA

-15V@35mA

+5V @ 200mA

C-3

2" x 4" x 0.4"

OBS

TIMING DIAGRAM

ADC-QM

--1

100nsec

MIN

Optional

Status or Busy

Output

Serial Data Output

Temperature Coefficient

Gain (of Reading)

Offset (Unipolar)

(Bipolar)

Power Required

Yes

OLE

+15V @ 25mA

-15V @ SOmA

+5V @ 300mA

Package Style

Package Size

Price (1-9)

ADC-SQM

ADC-10QM

ADC-12QM

$250.

$280.

$305.

ADC-SQU

ADC-10QU

ADC-12QU

$260.

$290.

$315.

I The desired input range is selected

the module terminals.

2 Input impedance

.Specifications

without

by the user with connections

and jumpers

buffer is proportional

to input voltage range.

same as for ADC-QM.

TIMING DIAGRAM

ADC-QU

CONVERT

COMMAND

--11-1O0n5

min

CONVERT

COMMAND

:vililllllllllllill

'IIIIIII'IIII

L-STATUS

CLOCK

-----

MSB

STATUS

CLOCK

2SB

11111111111

3SB

4SB

~"i

'0'

MSB

2Sa

3SB

4SB

'0'

r If I

r+-t

'0'

II I I I

'I'I'II'III

ri I1II1111

I I I I I I I I I I

I I I I I I I I I I I I I

I II"

III

5SB

(

5SB

I I I I I I I I I I I I I I

I I I I I I I I I I I I

"7l

II1I

'0' '1'

LSB

COMPARATOR

OUTPUT

j I ..;. I

:iJ,~IU

I I

LSB

-- - -- ----lT~

(

NEW CODE,

01010...1

CO~~~~,~!OR

RETURN TO ZERO

SERIAL OUTPUT

)

9 10 11 12

CODE, 10110...1

CONVERTERS

BLOCK DIAGRAM

ADC-QM & ADC-Q U

+15

JOK

.- v"

GAIN

-15

MSB

~::.;)~,.,.~.~",.""",..,i,."

OBS

+15V

~ 3MEG

REF

PRECJSION DAC .

(pDAC IC'S PLUS

THIN FILM RESISTOR

NETWORK)

> 4'VV'

ZERO

~ -15

OLE

BIP/UNI

II)

..J

MSB

+15V

2710--.

30 ~

GRD

COMP. OUT

-. STATUS

CONVERT CMD

CLOCK IN

CLOCK OUT

TTL

LOGIC

REGISTERS

STATUS

INTE RNAL

CLOCK

CLOCK INHIBIT

:: In the ADC-8QM

and ADC-8QU,

bit 8 is the LSB,

pins 48,50, 52 and 54 are deleted. In the ADC-10QM

ADC-10QU, bit 10 is the LSB, and pins 48 and 50

ieleted.