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OC-48/OC-48 FEC Clock and Data Recovery
IC with Integrated Limiting Amp
ADN2811
FEATURES
Meets SONET requirements for jitter transfer/generation/
tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
1.9 GHz minimum bandwidth
Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for both native SONET and
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs
(LVPECL/LVDS only at 155.52 MHz)
19.44 MHz on-chip oscillator to be used with external crystal
Loss of lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm, 48-lead LFCSP
PRODUCT DESCRIPTION
The ADN2811 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at OC-48 and
OC-48 FEC rates. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance. All
specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both the 2.48 Gb/s and
2.66 Gb/s digital wrapper rates are supported by the ADN2811,
without any change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
The ADN2811 is available in a compact, 7 mm × 7 mm, 48-lead
chip scale package.
APPLICATIONS
SONET OC-48, SDH STM-16, and 15/14 FEC
WDM transponders
Regenerators/repeaters
Test equipment
Backplane applications
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
VCC
VEE
CF1
CF2
LOL
2
PIN
QUANTIZER
NIN
ADN2811
LOOP
FILTER
/n
XTAL
OSC
2
2
REFSEL[0..1]
REFCLKP/N
XO1
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
XO2
VREF
LEVEL
DETECT
DATA
RETIMING
2
THRADJ
SDOUT
DATAOUTP/N
2
CLKOUTP/N
RATE
FRACTIONAL
DIVIDER
REFSEL
03019-B-001
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADN2811
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Functional Descriptions.......................... 6
Definition of Terms .......................................................................... 8
Maximum, Minimum, and Typical Specifications ................... 8
Input Sensitivity and Input Overdrive....................................... 8
Single-Ended vs. Differential ...................................................... 8
LOS Response Time ..................................................................... 9
Jitter Specifications....................................................................... 9
Theory of Operation ...................................................................... 10
Functional Description .................................................................. 12
Clock and Data Recovery .......................................................... 12
Limiting Amplifier ..................................................................... 12
Slice Adjust .................................................................................. 12
Loss of Signal (LOS) Detector .................................................. 12
Reference Clock.......................................................................... 12
Lock Detector Operation .......................................................... 13
Squelch Mode ............................................................................. 14
Test Modes: Bypass and Loopback........................................... 14
Applications Information .............................................................. 15
PCB Design Guidelines ............................................................. 15
Choosing AC-Coupling Capacitors ......................................... 17
DC-Coupled Application .......................................................... 18
LOL Toggling during Loss of Input Data................................ 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format.................................................................. Universal
Changes to Table 6 and Table 7......................................................13
Updated Outline Dimensions ........................................................19
Changes to Ordering Guide ...........................................................19
12/02—Data Sheet Changed from Rev. 0 to Rev. A.
Change to FUNCTIONAL DESCRIPTION Reference Clock ..10
Updated OUTLINE DIMENSIONS .............................................16
Rev. B | Page 2 of 20
ADN2811
SPECIFICATIONS
Table 1. T
A
= T
MIN
to T
MAX,
VCC = V
MIN
to V
MAX
, V
EE
= 0 V, C
F
= 4.7 µF, SLICEP = SLICEN = VCC, unless otherwise noted
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
Differential Input Sensitivity
Input Overdrive
Input Offset
Input rms Noise
QUANTIZER—AC CHARACTERISTICS
Upper –3 dB Bandwidth
Small Signal Gain
S11
Input Resistance
Input Capacitance
Pulse Width Distortion
2
QUANTIZER SLICE ADJUSTMENT
Gain
Control Voltage Range
Slice Threshold Offset
LEVEL SIGNAL DETECT (SDOUT)
Level Detect Range (See Figure 4)
Conditions
@ PIN or NIN, DC-Coupled
DC-Coupled. (See Figure 24)
PIN–NIN, AC-Coupled
1
, BER = 1 × 10
−10
Figure 6
BER = 1 × 10
−10
Min
0
0.4
4
2
500
244
1.9
54
−15
100
0.65
10
0.115
−0.8
1.3
0.200
0.300
+0.8
VCC
10
5
Typ
Max
1.2
2.4
Unit
V
V
V
mV p-p
mV p-p
µV
µV rms
GHz
dB
dB
Ω
pF
ps
V/V
V
V
mV
mV
mV
mV
µs
dB
dB
dB
µs
V
mA
kHz
dB
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
455
910
VCC
84
84
600
1200
VCC − 0.3
150
150
mV
mV
V
V
ps
ps
Differential
@ 2.5 GHz
Differential
SliceP–SliceN = ±0.5 V
SliceP–SliceN
@ SliceP or SliceN
±1.0
R
THRESH
= 2 kΩ
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
R
THRESH
= 2 kΩ
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
From f
VCO
error > 1000 ppm
3.0
150
PIN–NIN = 10 mV p-p
OC-48
OC-48
OC-48, 12 kHz–20 MHz
OC-48 (See Figure 11)
600 Hz
6 kHz
100 kHz
1 MHz
V
SE
(See Figure 5)
V
DIFF
(See Figure 5)
V
OH
V
OL
20% to 80%
80% to 20%
9.4
2.5
0.7
0.1
5.6
3.9
3.2
13.3
5.3
3.0
0.3
6.6
6.1
6.7
60
3.3
164
590
0.025
0.05
18.0
7.6
5.2
5
7.8
8.5
9.9
Response Time, DC-Coupled
Hysteresis (Electrical), PRBS 2
23
LOSS OF LOCK DETECT (LOL)
LOL Response Time
POWER SUPPLY VOLTAGE
POWER SUPPLY CURRENT
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
Jitter Peaking
Jitter Generation
Jitter Tolerance
3.6
215
880
0.003
3
0.09
92
3
20
3
5.5
1.0
3
300
600
VCC − 0.6
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
Rise Time
Fall time
Rev. B | Page 3 of 20
ADN2811
Parameter
Setup Time
Hold Time
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Common-Mode Level
TEST DATA DC INPUT CHARACTERISTICS
4
(TDINP/N)
Peak-to-Peak Differential Input Voltage
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Conditions
T
S
(See Figure 3) OC-48
T
H
(See Figure 3) OC-48
@ REFCLKP or REFCLKN
DC-Coupled, Single-Ended
CML Inputs
Min
140
150
0
100
VCC/2
0.8
V
IH
V
IL
V
IN
= 0.4 V or V
IN
= 2.4 V
V
OH
, I
OH
= −2.0 mA
V
OL
, I
OL
= +2.0 mA
2.0
−5
2.4
0.4
0.8
+5
Typ
Max
Unit
ps
ps
V
mV
V
V
V
V
µA
V
V
VCC
1
2
PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.
PWD measurement made on quantizer outputs in Bypass mode.
3
Measurement is equipment limited.
4
TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
Rev. B | Page 4 of 20
