AFBR-5903Z/5903EZ/5903AZ
FDDI, Fast Ethernet Transceivers
in 2 x 5 Package Style
Data Sheet
Description
The AFBR-5903Z family of transceivers from Avago Tech-
nologies provide the system designer with products
to implement a range of FDDI and ATM (Asynchronous
Transfer Mode) designs at the 100 Mb/s-125 MBd rate.
The transceivers are all supplied in the new industry
standard 2 x 5 DIP style with a MT-RJ fiber connector
interface.
Features
• Multisourced 2 x 5 package style with MT-RJ
receptacle
• Single +3.3 V power supply
• Wave solder and aqueous wash process compatible
• Full compliance with the optical performance
requirements of the FDDI PMD standard
• Full compliance with the FDDI LCF-PMD standard
• Full compliance with the optical performance
requirements of the ATM 100 Mb/s physical layer
• Full compliance with the optical performance
requirements of 100 Base-FX version of IEEE 802.3u
• “RoHS” compliance
• Receiver output squelch function enabled
FDDI PMD, ATM and Fast Ethernet 2 km Backbone Links
The AFBR-5903Z is a 1300 nm product with optical per-
formance compliant with the FDDI PMD standard. The
FDDI PMD standard is ISO/IEC 9314-3: 1990 and ANSI
X3.166 - 1990.
These transceivers for 2 km multimode fiber backbones
are supplied in the small 2 x 5 MT-RJ package style for
those designers who want to avoid the larger MIC/R
(Media Interface Connector/Receptacle) defined in the
FDDI PMD standard.
Avago Technologies also provides several other FDDI
products compliant with the PMD and SM-PMD standards.
These products are available with MIC/R, ST
©
, SC and FC
connector styles. They are available in the 1 x 9, 1 x 13 and
2 x 11 transceiver and 16 pin transmitter/receiver pack-
age styles for those designs that require these alternate
configurations.
The AFBR-5903Z is also useful for both ATM 100 Mb/s
interfaces and Fast Ethernet 100 Base-FX interfaces. The
ATM Forum User-Network Interface (UNI) Standard, Version
3.0, defines the Physical Layer for 100 Mb/s Multimode
Fiber Interface for ATM in Section 2.3 to be the FDDI PMD
Standard. Likewise, the Fast Ethernet Alliance defines the
Physical Layer for 100 Base-FX for Fast Ethernet to be the
FDDI PMD Standard.
ATM applications for physical layers other than 100
Mb/s Multimode Fiber Interface are supported by
Avago Technologies. Products are available for both
the single-mode and the multimode fiber SONET OC-3c
(STS-3c), SDH (STM-1) ATM interfaces and the 155 Mb/s-
194 MBd multimode fiber ATM interface as specified
in the ATM Forum UNI.
Applications
• Multimode fiber backbone links
• Multimode fiber wiring closet to desktop links
Ordering Information
The AFBR-5903Z 1300 nm product is available for pro-
duction orders through the Avago Technologies Com-
ponent Field Sales Offices and Authorized Distributors
world wide.
AFBR-5903Z
AFBR-5903EZ
AFBR-5903AZ
=
=
=
0°C to +70°C
No Shield
0°C to +70°C
Extended Shield
-40°C to +85°C
No Shield.
Contact your Avago Technologies sales representa-
tive for information on these alternative FDDI and ATM
products.
Transmitter Sections
The transmitter section of the AFBR-5903Z utilizes a 1300
nm Surface Emitting InGaAsP LED. This LED is packaged
in the optical subassembly portion of the transmitter
section. It is driven by a custom silicon IC which converts
differential PECL logic signals, ECL referenced (shifted) to
a +3.3 V supply, into an analog LED drive current.
Package
The overall package concept for the Avago Technologies
transceiver consists of the following basic elements; two
optical subassemblies, an electrical subassembly and the
housing as illustrated in Figure 1.
The package outline drawing and pin out are shown in Figures
2 and 3. The details of this package outline and pin out are
compliant with the multisource definition of the 2 x 5 DIP.
Receiver Sections
The low profile of the Avago Technologies transceiver design
The receiver section of the AFBR-5903Z utilizes an InGaAs complies with the maximum height allowed for the MT-RJ
PIN photodiode coupled to a custom silicon transimped- connector over the entire length of the package.
ance preamplifier IC. It is packaged in the optical sub-
The optical subassemblies utilize a high-volume assembly
assembly portion of the receiver.
process together with low-cost lens elements which result
This PIN/preamplifier combination is coupled to a custom in a cost-effective building block.
quantizer IC which provides the final pulse shaping for
The electrical subassembly consists of a high volume mul-
the logic output and the Signal Detect function. The Data
tilayer printed circuit board on which the IC and various
output is differential. The Signal Detect output is single-
surface-mounted passive circuit elements are attached.
ended. Both Data and Signal Detect outputs are PECL
compatible, ECL referenced (shifted) to a +3.3 V power The receiver section includes an internal shield for the elec-
supply. The receiver outputs, Data Out and Data Out Bar, trical and optical subassemblies to ensure high immunity to
are squelched at Signal Detect Deassert. That is, when the external EMI fields.
light input power decreases to a typical -38 dBm or less, The outer housing is electrically conductive and is at receiver
the Signal Detect Deasserts, i.e. the Signal Detect output signal ground potential. The MT-RJ port is molded of filled
goes to a PECL low state. This forces the receiver outputs, nonconductive plastic to provide mechanical strength
Data Out and Data Out Bar to go to steady PECL levels and electrical isolation. The solder posts of the Avago
High and Low respectively.
Technologies design are isolated from the internal circuit
of the transceiver.
The transceiver is attached to a printed circuit board with
the ten signal pins and the two solder posts which exit
the bottom of the housing. The two solder posts provide
the primary mechanical strength to withstand the loads
imposed on the transceiver by mating with the MT-RJ
connectored fiber cables.
R
X
SUPPLY
DATA OUT
DATA OUT
SIGNAL
DETECT
DATA IN
DATA IN
LED DRIVER IC
QUANTIZER IC
PIN PHOTODIODE
PRE-AMPLIFIER
SUBASSEMBLY
R
X
GROUND
T
X
GROUND
MT-RJ
RECEPTACLE
LED OPTICAL
SUBASSEMBLY
T
X
SUPPLY
Figure 1. Block Diagram.
2
13.97
(0.55)
MIN.
5.15
(0.20)
(PCB to OVERALL
RECEPTACLE CENTER
LINE)
FRONT VIEW
4.5 ±0.2
(0.177 ±0.008)
(PCB to OPTICS
CENTER LINE)
Case Temperature
Measurement Point
9.6
13.59
(0.535) (0.378)
MAX. MAX.
TOP VIEW
Pin 1
1.778
(0.07)
10.16
(0.4)
7.59
(0.299)
8.6
(0.339)
12
(0.472)
Ø1.5
(0.059)
17.778
(0.7)
+0
-0.2
(+000)
(0.024)
(-008)
Ø 0.61
7.112
(0.28)
49.56 (1.951) REF.
37.56 (1.479) MAX.
9.3
9.8
(0.386) (0.366)
MAX. MAX.
SIDE VIEW
Min 2.92
(0.115)
Ø 1.07
(0.042)
DIMENSIONS IN MILLIMETERS (INCHES)
NOTES:
1. THIS PAGE DESCRIBES THE MAXIMUM PACKAGE OUTLINE, MOUNTING STUDS, PINS AND THEIR RELATIONSHIPS TO EACH OTHER.
2. TOLERANCED TO ACCOMMODATE ROUND OR RECTANGULAR LEADS.
3. ALL 12 PINS AND POSTS ARE TO BE TREATED AS A SINGLE PATTERN.
4. THE MT-RJ HAS A 750 µm FIBER SPACING.
5. THE MT-RJ ALIGNMENT PINS ARE IN THE MODULE.
6. FOR SM MODULES, THE FERRULE WILL BE PC POLISHED (NOT ANGLED).
7. SEE MT-RJ TRANSCEIVER PIN OUT DIAGRAM FOR DETAILS.
Figure 2. Package Outline Drawing
Labelling Information
Note:
YYWW
COO
Manufactured WorkWeek
Country Of Origin (Philippines)
3
RX
TX
Mounting
Studs/Solder
Posts
Top
View
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
Figure 3. Pin Out Diagram.
o
o
o
o
o
1
2
3
4
5
10 o
9o
8o
7o
6o
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
TRANSMITTER DISABLE (LASER BASED PRODUCTS ONLY)
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
Pin Descriptions:
Pin 1 Receiver Signal Ground V
EE
RX:
Directly connect this pin to the receiver ground plane.
Pin 7 Transmitter Signal Ground V
EE
TX:
Directly connect this pin to the transmitter ground
plane.
Pin 2 Receiver Power Supply V
CC
RX:
Pin 8 Transmitter Disable T
DIS
:
Provide +3.3 V dc via the recommended receiver power
supply filter circuit. Locate the power supply filter circuit No internal connection. Optional feature for laser based
products only. For laser based products connect this pin
as close as possible to the V
CC
RX pin.
to +3.3 V TTL logic high “1” to disable module. To enable
module connect to TTL logic low “0”.
Pin 3 Signal Detect SD:
Normal optical input levels to the receiver result in a logic
Pin 9 Transmitter Data In TD+:
“1” output.
No internal terminations are provided. See recommended
Low optical input levels to the receiver result in a fault circuit schematic.
condition indicated by a logic “0” output.
This Signal Detect output can be used to drive a PECL
Pin 10 Transmitter Data In Bar TD-:
input on an upstream circuit, such as Signal Detect input No internal terminations are provided. See recommended
or Loss of Signal-bar.
circuit schematic.
Pin 4 Receiver Data Out Bar RD-:
Mounting Studs/Solder Posts
No internal terminations are provided. See recommended The mounting studs are provided for transceiver mechani-
circuit schematic.
cal attachment to the circuit board. It is recommended
that the holes in the circuit board be connected to chassis
Pin 5 Receiver Data Out RD+:
ground.
No internal terminations are provided. See recommended
circuit schematic.
Pin 6 Transmitter Power Supply V
CC
TX:
Provide +3.3 V dc via the recommended transmitter power
supply filter circuit. Locate the power supply filter circuit
as close as possible to the V
CC
TX pin.
4
Application Information
OPTICAL POWER BUDGET (dB)
12
10
8
6
4
2
0
HFBR-5903
50/125 µm
HFBR-5903, 62.5/125 µm
The Applications Engineering group is available to assist
you with the technical understanding and design trade-offs
associated with these transceivers. You can contact them
through your Avago Technologies sales representative.
The following information is provided to answer some of the
most common questions about the use of these parts.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available optical power
for a fiber optic link to accommodate fiber cable losses plus
losses due to in-line connectors, splices, optical switches,
and to provide margin for link aging and unplanned losses
due to cable plant reconfiguration or repair.
Figure 4 illustrates the predicted OPB associated with the
transceiver specified in this data sheet at the Beginning
of Life (BOL). These curves represent the attenuation and
chromatic plus modal dispersion losses associated with
the 62.5/125 µm and 50/125 µm fiber cables only. The area
under the curves represents the remaining OPB at any link
length, which is available for overcoming non-fiber cable
related losses.
Avago Technologies LED technology has produced 1300
nm LED devices with lower aging characteristics than nor-
mally associated with these technologies in the industry.
The industry convention is 1.5 dB aging for 1300 nm LEDs.
The Avago Technologies 1300 nm LEDs will experience less
than 1 dB of aging over normal commercial equipment
mission life periods. Contact your Avago Technologies
sales representative for additional details.
1.0
1.5
2.0
0.3 0.5
FIBER OPTIC CABLE LENGTH (km)
2.5
Figure 4. Typical Optical Power Budget at BOL versus Fiber Optic Cable
Length.
Figure 4 was generated with a Avago Technologies fiber
optic link model containing the current industry conven-
tions for fiber cable specifications and the FDDI PMD
and LCF-PMD optical parameters. These parameters are
reflected in the guaranteed performance of the trans-
ceiver specifications in this data sheet. This same model
has been used extensively in the ANSI and IEEE commit-
tees, including the ANSI X3T9.5 committee, to establish
the optical performance requirements for various fiber
optic interface standards. The cable parameters used
come from the ISO/IEC JTC1/SC 25/WG3 Generic Cabling
for Customer Premises per DIS 11801 document and the
EIA/TIA-568-A Commercial Building Telecommunications
Cabling Standard per SP-2840.
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