Am29DL322D/323D/324D
Data Sheet
This product has been retired and is not available for designs. For new and current designs involving TSOP pack-
ages, S29JL032H supersedes Am29DL32xD and is the factory-recommended migration path. Please refer to the
S29JL032H Datasheet for specifications and ordering information.
For new and current designs involving Fine-pitch BGA (FBGA) packages, S29PL032J supersedes Am29DL32xD
and is the factory-recommended migration path. Please refer to the S29PL032J Datasheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes only.
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
21534
Revision
D
Amendment
+8
Issue Date
December 13, 2005
Am29DL322D/323D/324D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
This product has been retired and is not available for designs. For new and current designs involving TSOP packages, S29JL032H supersedes Am29DL32xD and is the factory-recom-
mended migration path. Please refer to the S29JL032H Datasheet for specifications and ordering information.
For new and current designs involving Fine-pitch BGA (FBGA) packages, S29PL032J supersedes Am29DL32xD and is the factory-recommended migration path. Please refer to the
S29PL032J Datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank.
— Zero latency between read and write operations
■
Multiple bank architectures
— Three devices available with different bank sizes
(refer to Table 3)
■
SecSi
TM
(Secured Silicon) Sector
— Current version of device has 64 Kbytes; future
versions will have 256 bytes
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
■
Package options
— 63-ball FBGA
— 48-pin TSOP
■
Top or bottom boot block
■
Manufactured on 0.23 µm process technology
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast 70 ns
— Program time: 7 µs/word typical utilizing Accelerate
function
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Minimum 1 million write cycles guaranteed per
sector
■
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■
Supports Common Flash Memory Interface (CFI)
■
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
■
WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
— Acceleration (ACC) function accelerates program
timing
■
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
Publication#
21534
Rev:
D
Amendment/+8
Issue Date:
December 13, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29DL322D/323D/324D family consists of
32 megabit, 3.0 volt-only flash memory devices, orga-
nized as 2,097,152 words of 16 bits each or 4,194,304
bytes of 8 bits each. Word mode data appears on
DQ0–DQ15; byte mode data appears on DQ0–DQ7.
The device is designed to be programmed in-system
with the standard 3.0 volt V
CC
supply, and can also be
programmed in standard EPROM programmers.
The devices are available with an access time of 70,
90 or 120 ns. The devices are offered in 48-pin TSOP
and 63-ball FBGA packages. Standard control
pins—chip enable (CE#), write enable (WE#), and out-
put enable (OE#)—control normal read and write
operations, and avoid bus contention issues.
The devices requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Sector as bonus space, reading and writing like any
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s y s t e m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a
programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL32xD device family uses multiple bank
architectures to provide flexibility for different applica-
tions. Three devices are available with the following
bank sizes:
Device
DL322
DL323
DL324
Bank 1
4
8
16
Bank 2
28
24
16
Am29DL322D/323D/324D Features
The
SecSi
TM
(Secured Silicon) Sector
is an extra sector
capable of being permanently locked by AMD or cus-
tomers. The
SecSi Indicator Bit
(DQ7) is
permanently set to a 1 if the part is
factory locked,
and set to a 0 if
customer lockable.
This way, cus-
tomer lockable parts can never be used to replace a
factory locked part.
Current version of device has 64
Kbytes; future versions will have only 256 bytes.
This should be considered during system design.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
2
Am29DL322D/323D/324D
December 13, 2005
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .......................... 8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Word/Byte Configuration .............................................................. 10
Requirements for Reading Array Data ......................................... 10
Writing Commands/Command Sequences .................................. 11
Simultaneous Read/Write Operations
with Zero Latency .........................................................................11
Standby Mode .............................................................................. 11
Automatic Sleep Mode .................................................................11
RESET#: Hardware Reset Pin .....................................................12
Output Disable Mode ...................................................................12
Autoselect Mode .......................................................................... 17
Sector/Sector Block Protection and Unprotection ........................ 18
Write Protect (WP#) .....................................................................19
Temporary Sector Unprotect ........................................................19
Figure 1. Temporary Sector Unprotect Operation................................. 19
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms ............................................................ 20
DQ6: Toggle Bit I .......................................................................... 32
Figure 6. Toggle Bit Algorithm .............................................................. 32
DQ2: Toggle Bit II ......................................................................... 33
Reading Toggle Bits DQ6/DQ2 .................................................... 33
DQ5: Exceeded Timing Limits ...................................................... 33
DQ3: Sector Erase Timer ............................................................. 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform............................. 35
Figure 8. Maximum Positive Overshoot Waveform .............................. 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents).................................................................... 37
Figure 10. Typical I
CC1
vs. Frequency................................................... 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup .......................................................................... 38
Figure 12. Input Waveforms and Measurement Levels ........................ 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Read Operation Timings...................................................... 39
Figure 14. Reset Timings...................................................................... 40
Word/Byte Configuration (BYTE#) ............................................... 41
Figure 15. BYTE# Timings for Read Operations .................................. 41
Figure 16. BYTE# Timings for Write Operations .................................. 41
Erase and Program Operations ................................................... 42
Figure 17. Program Operation Timings ................................................
Figure 18. Accelerated Program Timing Diagram ................................
Figure 19. Chip/Sector Erase Operation Timings .................................
Figure 20. Back-to-back Read/Write Cycle Timings .............................
Figure 21. Data# Polling Timings (During Embedded Algorithms) .......
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............
Figure 23. DQ2 vs. DQ6 .......................................................................
43
43
44
45
45
46
46
SecSi
TM
(Secured Silicon) Sector
Flash Memory Region ..................................................................21
Hardware Data Protection ............................................................22
Common Flash Memory Interface (CFI) . . . . . . . 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ......................................................................25
Reset Command ..........................................................................26
Autoselect Command Sequence ..................................................26
Enter SecSi
TM
Sector/Exit SecSi Sector
Command Sequence ...................................................................26
Byte/Word Program Command Sequence ................................... 26
Figure 3. Program Operation ................................................................ 27
Temporary Sector Unprotect ........................................................ 47
Figure 24. Temporary Sector Unprotect Timing Diagram..................... 47
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram 48
Alternate CE# Controlled Erase and Program Operations ........... 49
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 50
Chip Erase Command Sequence .................................................27
Sector Erase Command Sequence ..............................................28
Erase Suspend/Erase Resume Commands ................................ 28
Figure 4. Erase Operation..................................................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ......................................................................31
Figure 5. Data# Polling Algorithm ......................................................... 31
Erase And Programming Performance . . . . . . . 51
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 51
TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 51
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 52
FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm . 52
TS 048—48-Pin Standard TSOP ................................................. 53
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 54
RY/BY#: Ready/Busy# ................................................................. 32
December 13, 2005
Am29DL322D/323D/324D
3
PRODUCT SELECTOR GUIDE
Part Number
Speed Option
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
Regulated Voltage Range: V
CC
= 3.0–3.6 V
Standard Voltage Range: V
CC
= 2.7–3.6 V
70
70
30
Am29DL322D/323D/324D
70R
90
90
90
40
120
120
120
50
BLOCK DIAGRAM
OE# BYTE#
V
CC
V
SS
Y-Decoder
A20–A0
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A20–A0
RESET#
WE#
CE#
BYTE#
WP#/ACC
DQ15–DQ0
A20–A0
STATE
CONTROL
&
COMMAND
REGISTER
X-Decoder
Status
DQ15–DQ0
Control
DQ15–DQ0
X-Decoder
Lower Bank
A20–A0
Lower Bank Address
OE# BYTE#
4
Am29DL322D/323D/324D
Latches and
Control Logic
Y-Decoder
DQ15–DQ0
A20–A0
December 13, 2005
模拟与混合信号
