This product has been retired and is not recommended for designs. For new and current designs,
S29PL127J supersedes Am29PDL127H and is the factory-recommended migration path. Please refer
to the S29PL127J datasheet for specifications and ordering information. Availability of this document
is retained for reference and historical purposes only.
June 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
26864
Revision
A
Amendment
+6
Issue Date
June 07, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY
Am29PDL127H
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write
Flash Memory with Enhanced VersatileIO
TM
Control
This product has been retired and is not recommended for designs. For new and current designs, S29PL127J supersedes Am29PDL127H and is the factory-recommended migration path.
Please refer to the S29PL127J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random
locations within the page
— 18 mA program/erase current
— 1 µA typical standby mode current
SOFTWARE FEATURES
■
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
■
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and program
operations for battery-powered applications
■
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
■
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
■
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
■
FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
per device
— Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank B: 48 Mbit (32 Kw x 96)
— Bank C: 48 Mbit (32 Kw x 96)
— Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
■
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase
cycle completion
■
Enhanced VersatileI/O
TM
(V
IO
) Control
— Output voltage generated and input voltages tolerated on all
control inputs and I/Os is determined by the voltage on the
V
IO
pin
— V
IO
options at 1.8 V and 3 V I/O
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
■
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
■
WP#/ ACC (Write Protect/Acceleration) input
— At V
IL
, hardware level protection for the first and last two 4K
word sectors.
— At V
IH
, allows removal of sector protection
— At V
HH
, provides accelerated programming in a factory
setting
■
Both top and bottom boot blocks in one device
■
Manufactured on 0.13 µm process technology
■
20-year data retention at 125°C
■
Minimum 1 million erase cycle guarantee per sector
■
Persistent Sector Protection
— A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
— Sectors can be locked and unlocked in-system at V
CC
level
PERFORMANCE CHARACTERISTICS
■
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
■
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
■
Power consumption (typical values at 10 MHz)
— 45 mA active read current
■
Package options
— 80-ball Fine-pitch BGA
— Multi Chip Packages (MCP)
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
26864
Rev:
A
Amendment/+6
Issue Date:
June 07, 2005
P R E L I M I N A R Y
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random
locations within the page
— 18 mA program/erase current
— 1 µA typical standby mode current
SOFTWARE FEATURES
■
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
■
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and program
operations for battery-powered applications
■
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
■
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
■
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
■
FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
per device
— Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank B: 48 Mbit (32 Kw x 96)
— Bank C: 48 Mbit (32 Kw x 96)
— Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
■
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase
cycle completion
■
Enhanced VersatileI/O
TM
(V
IO
) Control
— Output voltage generated and input voltages tolerated on all
control inputs and I/Os is determined by the voltage on the
V
IO
pin
— V
IO
options at 1.8 V and 3 V I/O
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
■
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
■
WP#/ ACC (Write Protect/Acceleration) input
— At V
IL
, hardware level protection for the first and last two 4K
word sectors.
— At V
IH
, allows removal of sector protection
— At V
HH
, provides accelerated programming in a factory
setting
■
Both top and bottom boot blocks in one device
■
Manufactured on 0.13 µm process technology
■
20-year data retention at 125°C
■
Minimum 1 million erase cycle guarantee per sector
■
Persistent Sector Protection
— A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
— Sectors can be locked and unlocked in-system at V
CC
level
PERFORMANCE CHARACTERISTICS
■
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
■
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
■
Power consumption (typical values at 10 MHz)
— 45 mA active read current
■
Package options
— 80-ball Fine-pitch BGA
— Multi Chip Packages (MCP)
2
Am29PDL127H
June 07, 2005
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29PDL127H is a 128 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 8 Mwords. The device is offered in an 80-ball
Fine-pitch BGA package, and various multi-chip packages.
The word-wide data (x16) appears on DQ15-DQ0. This de-
vice can be programmed in-system or in standard EPROM
programmers. A 12.0 V V
PP
is not required for write or erase
operations.
The device offers fast page access times of 20 to 30 ns, with
corresponding random access times of 55 to 70 ns, respec-
tively, allowing high speed microprocessors to operate with-
out wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#) and output
