Features
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Utilizes the ARM7TDMI
™
ARM Thumb Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
2K Bytes Internal RAM
Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8/16-bit External Data Bus
Multi-processor Interface (MPI)
– High-performance External Processor Interface
– 512 x 16-bit Dual-port RAM
8-channel Peripheral Data Controller
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request
58 Programmable I/O Lines
6-channel 16-bit Timer/Counter
– 6 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
3 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
– Support for Up to 9-bit Data Transfers
Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8- to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Power Management Controller (PMC)
– CPU and Peripherals Can Be Deactivated Individually
IEEE 1149.1 JTAG Boundary-scan on All Active Pins
Fully Static Operation: 0 Hz to 25 MHz (12 MHz at 1.8V)
1.8V to 3.6V Core Operating Voltage Range
2.7V to 5.5V I/O Operating Voltage Range
-40°C to +85°C Operating Temperature Range
Available in a 176-lead TQFP Package
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AT91
ARM
®
Thumb
®
Microcontrollers
AT91M63200
Summary
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Description
The AT91M63200 is a member of the Atmel AT91 16/32-bit microcontroller family
which is based on the ARM7TDMI processor core.
This processor has a high-performance 32-bit RISC architecture with a high-density
16-bit instruction set and very low power consumption. In addition, a large number of
internally banked registers result in very fast exception handling, making the device
ideal for real-time control applications. The AT91 ARM-based MCU family also fea-
tures Atmel’s high-density, in-system programmable, nonvolatile memory technology.
The AT91M63200 has a direct connection to off-chip memory, including Flash,
through the External Bus Interface.
The Multi-processor Interface (MPI) provides a high-performance interface with an
external coprocessor or a high bandwidth peripheral.
The AT91M63200 is manufactured using the Atmel high-density CMOS technology.
By combining the ARM7TDMI microcontroller core with on-chip SRAM, a multi-pro-
cessor interface and a wide range of peripheral functions on a monolithic chip, the
AT91M63200 provides a highly-flexible and cost-effective solution to many compute-
intensive multi-processor applications.
Rev. 1028DS–06/00
1
Pin Configuration
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
AT91M63200
GND
GND
NCS0
NCS1
NCS2
NCS3
NLB/A0
A1
A2
A3
A4
A5
A6
A7
VDDIO
GND
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
VDDIO
GND
A20/CS7
A21/CS6
A22/CS5
A23/CS4
D0
D1
D2
D3
D4
D5
D6
D7
VDDCORE
VDDIO
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
AT91M63200
GND
GND
D8
D9
D10
D11
D12
D13
D14
D15
PB19/TCLK0
PB20/TIOA0
PB21/TIOB0
PB22/TCLK1
VDDIO
GND
PB23/TIOA1
PB24/TIOB1
PB25/TCLK2
PB26/TIOA2
PB27/TIOB2
PA0/TCLK3
PA1/TIOA3
PA2/TIOB3
PA3/TCLK4
PA4/TIOA4
PA5/TIOB4
PA6/TCLK5
VDDIO
GND
PA7/TIOA5
PA8/TIOB5
PA9/IRQ0
PA10/IRQ1
PA11/IRQ2
PA12/IRQ3
PA13/FIQ
PA14/SCK0
PA15/TXD0
PA16/RXD0
PA17/SCK1
PA18/TXD1/NTRI
VDDCORE
VDDIO
Pin
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
AT91M63200
GND
GND
PA19 / RXD1
PA20 / SCK2
PA21 / TXD2
PA22 / RXD2
PA23 / SPCK
PA24/MISO
PA25/MOSI
PA26/NPCS0/NSS
PA27/NPCS1
PA28/NPCS2
PA29/NPCS3
MPI_A1
VDDIO
GND
MPI_A2
MPI_A3
MPI_A4
MPI_A5
MPI_A6
MPI_A7
MPI_A8
MPI_A9
MPI_NCS
MPI_RNW
MPI_BR
MPI_BG
VDDIO
GND
MPI_D0
MPI_D1
MPI_D2
MPI_D3
MPI_D4
MPI_D5
MPI_D6
MPI_D7
MPI_D8
MPI_D9
MPI_D10
MPI_D11
VDDCORE
VDDIO
Pin
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
AT91M63200
GND
GND
MPI_D12
MPI_D13
MPI_D14
MPI_D15
PB0/MPI_NOE
PB1/MPI_NLB
PB2/MPI_NUB
PB3
PB4
PB5
PB6
PB7
VDDIO
GND
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17/MCKO
NWDOVF
MCKI
VDDIO
GND
PB18/BMS
JTAGSEL
TMS
TDI
TDO
TCK
NTRST
NRST
NWAIT
NOE/NRD
NWE/NWR0
NUB/NWR1
VDDCORE
VDDIO
2
AT91M63200
AT91M63200
Pin Description
Module
Name
A0 - A23
D0 - D15
CS4 - CS7
NCS0 - NCS3
NWR0
NWR1
EBI
NRD
NWE
NOE
NUB
NLB
NWAIT
BMS
MPI_NCS
MPI_RNW
MPI_BR
MPI_BG
MPI
MPI_NOE
MPI_NLB
MPI_NUB
MPI_A1 - MPI_A9
MPI_D0 - MPI_D15
AIC
IRQ0 - IRQ3
FIQ
TCLK0 - TCLK5
Timer
TIOA0 - TIOA5
TIOB0 - TIOB5
SCK0 - SCK2
USART
TXD0 - TXD2
RXD0 - RXD2
SPCK
MISO
SPI
MOSI
NSS
NPCS0 - NPCS3
PIO
WD
Clock
Reset
PA0 - PA29
PB0 - PB27
NWDOVF
MCKI
MCKO
NRST
Function
Address Bus
Data Bus
Chip Select
Chip Select
Lower Byte 0 Write Signal
Lower Byte 1 Write Signal
Read Signal
Write Enable
Output Enable
Upper Byte Select (16-bit SRAM)
Lower Byte Select (16-bit SRAM)
Wait Input
Boot Mode Select
Chip Select
Read Not Write Signal
Bus Request From External
Processor
Bus Grant To External Processor
Output Enable
Lower Byte Select
Upper Byte Select
Address Bus
Data Bus
External Interrupt Request
Fast External Interrupt Request
Timer External Clock
Multipurpose Timer I/O Pin A
Multipurpose Timer I/O Pin B
External Serial Clock
Transmit Data Output
Receive Data Input
SPI Clock
Master In Slave Out
Master Out Slave In
Slave Select
Peripheral Chip Select
Programmable I/O Port A
Programmable I/O Port B
Watchdog Timer Overflow
Master Clock Input
Master Clock Output
Hardware Reset Input
Type
Output
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
I/O
Input
Input
Input
I/O
I/O
I/O
Output
Input
I/O
I/O
I/O
Input
Output
I/O
I/O
Output
Input
Output
Input
Active
Level
–
–
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
–
Low
–
High
High
Low
Low
Low
–
–
–
–
–
–
–
–
–
–
–
–
–
Low
Low
–
–
Low
–
–
Low
Schmitt trigger, internal pull-up
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
Input after reset
Input after reset
Open-drain
Schmitt trigger
Sampled during reset
Used in Byte Write option
Used in Byte Write option
Used in Byte Write option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
A23 - A20 after reset
Comments
All valid after reset
3
Pin Description (Continued)
Module
Name
Function
Type
Active
Level
Comments
High enables IEEE 1149.1 JTAG
Boundary-scan
Low enables ARM Standard ICE
debug
Schmitt trigger, internal pull-up
Schmitt trigger, internal pull-up
Schmitt trigger, internal pull-up
Schmitt trigger, internal pull-up
3V or 5V nominal supply
2.0V or 3V nominal supply
Sampled during reset
JTAGSEL
Selects between JTAG and ICE Mode
Input
–
JTAG/ICE
TMS
TDI
TDO
TCK
NTRST
VDDIO
Test Mode Select
Test Data In
Test Data Out
Test Clock
Test Reset Input
I/O Power
Core Power
Ground
Tri-state Mode Enable
Input
Input
Output
Input
Input
Power
Power
Ground
Input
–
–
–
–
Low
–
–
–
Low
Power
Emulation
VDDCORE
GND
NTRI
Figure 1.
Pin Configuration (Top View)
176
1
AT91M63X00
176-Lead TQFP
133
132
44
45
88
89
4
AT91M63200
AT91M63200
Block Diagram
NTRST
TMS
TDO
TDI
TCK
Reset
NRST
JTAG
Embedded
ICE
MPI_A1-MPI_A9
MPI_D0-MPI_D15
MPI_NCS
MPI_RNW
MPI_BR
MPI_BG
P
I
O
Internal RAM
2/8K Bytes
EBI: External
Bus Interface
PB0/MPI_NOE
PB1/MPI_NLB
PB2/MPI_NUB
D0-D15
A1-A19
A0/NLB
NRD/NOE
NWR0/NWE
NWR1/NUB
NWAIT
NCS0-NCS3
A20/CS7
A21/CS6
A22/CS5
A23/CS4
PB18/BMS
ARM7TDMI Core
MCKI
PB17/MCKO
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PA9/IRQ0
PA10/IRQ1
PA11/IRQ2
PA12/IRQ3
PA13/FIQ
PA14/SCK0
PA15/TXD0
PA16/RXD0
PA17/SCK1
PA18/TXD1/NTRI
PA19/RXD1
PA20/SCK2
PA21/TXD2
PA22/RXD2
PA23/SPCK
PA24/MISO
PA25/MOSI
PA26/NPCS0/NSS
PA27/NPCS1
PA28/NPCS2
PA29/NPCS3
P
I
O
ASB
Clock
ASB
Controller
AMBA Bridge
AIC: Advanced
Interrupt Controller
EBI User
Interface
USART0
2 PDC
Channels
APB
2 PDC
Channels
2 PDC
Channels
PMC: Power
Management
Controller
Chip ID
TC: Timer
Counter
Block 0
TC0
TC1
TC2
TC: Timer
Counter
Block 1
TC0
TC1
P
I
O
MPI: Multi-
Processor
Interface
PB19/TCLK0
PB22/TCLK1
PB25/TCLK2
PB20/TIOA0
PB21/TIOB0
PB23/TIOA1
PB24/TIOB1
PB26/TIOA2
PB27/TIOB2
PA0/TCLK3
PA3/TCLK4
PA6/TCLK5
PA1/TIOA3
PA2/TIOB3
PA4/TIOA4
PA5/TIOB4
PA7/TIOA5
PA8/TIOB5
USART1
USART2
SPI: Serial
Peripheral
Interface
2 PDC
Channels
TC2
NWDOVF
WD: Watchdog
Timer
PIOA: Parallel I/O
Controller A
PIOB: Parallel I/O
Controller B
5
