Features
•
ARM7TDMI
®
ARM
®
Thumb
®
Processor Core
– High Performance 32-bit RISC
– High-density 16-bit Instruction set (Thumb)
– Leader in MIPS/Watt
– Embedded ICE (In Circuit Emulation)
16 Kbytes Internal SRAM
Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 6 Mbytes, Up to Four Chip Select Lines
8-level Priority, Vectored Interrupt Controller
– Three External Interrupts Including One Fast Interrupt Line
Ten Channel Peripheral Data Controller (PDC)
57 Programmable I/O Lines
Four 16-bit General Purpose Timers (GPT)
– Three Configurable Modes: Counter, PWM, Capture
– Four External Clock Inputs, Three Multi-purpose I/O Pins per Timer
Four 16-bit Simple Timers (ST)
Four Channel 16-bit Pulse Width Modulation (PWM)
Four CAN Controllers 2.0A and 2.0B Full CAN
– One with 32 Buffers, Three with 16 Buffers
Two USARTs
– Support for J1587 and LIN Protocols
One Master/Slave SPI Interface
– 8 to 16-bit Programmable Data Length
– Four External Serial Peripheral Chip Selects
Two 8-channel 10-bit Analog to Digital Converters (ADC)
Two 16-bit Capture Modules (CAPT)
Programmable Watch Timer (WT)
Programmable Watchdog (WD)
Power Management Controller (PMC)
– 32 kHz Oscillator, Main Oscillator and PLL
IEEE 1149.1 JTAG Boundary-scan on all Digital Pins
Fully Static Operation: 0 Hz to 30 MHz at VDDCORE=3.3V, 85°C
3.0V to 5.5V Operating Voltage Range
3.0V to 3.6V Core, Memory and Analog Voltage Range
-40° to +85°C Operating Temperature Range
Available in a 176-lead LQFP Package
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AT91 ARM
®
Thumb
®
- based
Microcontrollers
AT91SAM7A2
Summary
Description
The AT91SAM7A2 is based on the ARM7TDMI embedded processor. This processor
has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction
set and very low power consumption.
In addition, a large number of internally banked registers result in very fast exception
handling, making the device ideal for real-time control applications.
The AT91SAM7A2 has a direct connection to off-chip memory, including Flash,
through the fully programmable External Bus Interface.
An 8-level priority vectored Interrupt Controller in conjunction with the Peripheral Data
Controller significantly improves the real time performance of the device. The device is
manufactured using high-density CMOS technology.
By combining the ARM7TDMI processor with an on-chip SRAM, and a wide range of
peripheral functions, including USART, SPI, CAN Controllers, Timer Counter and Ana-
log-to-Digital Converters, on a monolithic chip, the AT91SAM7A2 is a powerful device
that provides a flexible, cost-effective solution to many compute-intensive embedded
control applications in the automotive and industrial world.
6021BS–ATARM–07/04
PRELIMINARY
PRELIMINARY
Block Diagram
Figure 1.
Block Diagram
5V
VDDCORE
SCANEN
IRQ[1:0]
3V
VDDIO
GND
I/O Power
Supply
Core Power
Supply
Generic
Interrupt
Controller
SPI
TEST
GND
TMS
TDO
TCK
FIQ
TDI
Select
JTAG
Advanced
Memory
Controller
EBI
SPCK/MPIO
MISO/MPIO
MOSI/MPIO
NPCS0/MPIO
NPCS1/MPIO
NPCS2/MPIO
NPCS3/MPIO
RXD0/MPIO
TXD0/MPIO
SCK0/MPIO
RXD1/MPIO
TXD1/MPIO
SCK1/MPIO
Embedded
ICE
Arbiter
ASB Controller
SFM
AMBA
TM
Bridge
ARM7TDMI
Core
PIO
2 PDC
Channels
USART0
2 PDC
Channels
USART1
2 PDC
Channels
Timer T0
10 Channel
PDC
Controller
ADD[19:1]
ADD0/NLB
ADD20/CS3
NOE/NRD
NWR0/NWE 3V
NWR1/NUB
NWAIT/UPIO
NCS[2:0]
D[15:0]
Internal SRAM
16 KB
Reset
NRESET
5V
PIO
PIO
Watch Dog
CLK/UPIO
RTCKI
RTCKO
MCKI
MCKO
LFCLK
Simple Timers
Watch Timer
CORECLK
ST0
CH0
CH1
5V
T0TIOA0/MPIO
T0TIOB0/MPIO
T0TCLK0/MPIO
T0TIOA1/MPIO
T0TIOB1/MPIO
T0TCLK1/MPIO
T0TIOA2/MPIO
T0TIOB2/MPIO
T0TCLK2/MPIO
Clock
Controller
with PLL
PIO TC0
PIO TC1
ST1
PIO TC2
CH0
CH1
Capture 0
PDC Channel
Timer T1
PLLRC
3V
CAPT0
T1TIOA0/MPIO
T1TIOB0/MPIO
T1TCLK0/MPIO
Capture 1
PIO
TC0
CAPT1
PDC Channel
PWM
5V
PWM0
PWM1
PWM2
PWM3
PIO[31:0]
UPIO
1 PDC
Channel
1 PDC
Channel
CAN0
ADC0
ADC1
8-channel 8-channel
10-bit ADC 10-bit ADC
Full Speed
16 Buffers
CAN1
Full Speed
16 Buffers
CAN2
CAN3
CH0
CH1
CH2
CH3
Analog
Power
Suppy
Full Speed Full Speed
32 Buffers 16 Buffers
CANRX3
VDDANA
CANRX0
CANRX1
CANRX2
CANTX0
CANTX1
ANA0IN[7:0]
Analog
ANA1IN[7:0]
5V
2
AT91SAM7A2 - Summary
6021BS–ATARM–07/04
CANTX2
CANTX3
VREFP0
VREFP1
GND
AT91SAM7A2 - Summary
Pin Configuration
Table 1.
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
VDDIO
IRQ0
IRQ1
FIQ
SCK0/MPIO
TXD0/MPIO
RXD0/MPIO
SCK1/MPIO
TXD1/MPIO
RXD1/MPIO
VDDCORE
CANTX3
CANRX3
CAPT0
CAPT1
SPCK/MPIO
MISO/MPIO
MOSI/MPIO
NPCS0/MPIO
VDDIO
GND
NPCS1/MPIO
NPCS2/MPIO
NPCS3/MPIO
T0TIOA0/MPIO
T0TIOB0/MPIO
T0TCLK0/MPIO
T0TIOA1/MPIO
T0TIOB1/MPIO
T0TCLK1/MPIO
T0TIOA2/MPIO
T0TIOB2/MPIO
VDDIO
GND
T0TCLK2/MPIO
T1TIOA0/MPIO
T1TIOB0/MPIO
T1TCLK0/MPIO
NRESET
UPIO0
UPIO1
UPIO2
UPIO3
UPIO4
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Name
GND
VDDIO
UPIO5
UPIO6
GND
VDDIO
UPIO7
UPIO 8
UPIO 9
UPIO 10
UPIO 11
UPIO 12
UPIO 13
UPIO 14
UPIO 15
UPIO 16
UPIO 17
UPIO 18
GND
VDDIO
UPIO19
UPIO20
UPIO21
UPIO22
UPIO23
UPIO24
UPIO25
UPIO26
UPIO27
UPIO28
UPIO29
UPIO30/NWAIT
UPIO31/CORECLK
CANTX0
CANRX0
CANTX1
CANRX1
CANTX2
CANRX2
PWM0
PWM1
PWM2
PWM3
GND
Pin
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Name
VDDIO
VDDANA
VREFP0
ANA0IN0
ANA0IN1
ANA0IN2
ANA0IN3
ANA0IN4
ANA0IN5
ANA0IN6
GND
VDDANA
ANA0IN7
VREFP1
ANA1IN0
ANA1IN1
ANA1IN2
ANA1IN3
ANA1IN4
ANA1IN5
ANA1IN6
ANA1IN7
GND
VDDCORE
RTCKI
RTCKO
GND
VDDCORE
SCANEN
TEST
TMS
TDO
TDI
TCK
GND
PLLRC
VDDCORE
MCKI
MCKO
GND
NWR1/NUB
D8
D1
D0
Pin
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
55
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Name
NOE/NRD
NCS0
ADD1
D9
D2
VDDCORE
D10
D3
D11
D4
D12
D5
D13
D6
D14
D7
D15
GND
ADD0/NLB
ADD17
ADD16
ADD15
ADD14
ADD13
ADD12
ADD11
ADD10
ADD9
ADD20/CS3
VDDCORE
NWR0/NWE
NCS2
NCS1
ADD19
ADD18
ADD8
ADD7
ADD6
ADD2
ADD3
ADD4
ADD5
GND
GND
PRELIMINARY
6021BS–ATARM–07/04
3
PRELIMINARY
Figure 2.
Pin Configuration
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
4
AT91SAM7A2 - Summary
6021BS–ATARM–07/04
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
AT91SAM7A2 - Summary
Signal Description
Table 2.
Signal Description
Module
Name
ADD[19:1]
ADD0/NLB
ADD20/CS3
D[15:0]
EBI
NOE
NWR0/NWE
NCS[2:0]
NWR1/NUB
NWAIT
CORECLK
IRQ[1:0]
GIC
FIQ
Power-on
Reset
NRESET
MCKI
Master Clock MCKO
PLLRC
32.768 kHz
clock
PIO
RTCKI
RTCKO
UPIO[31:0]
SCK0/MPIO
USART0
RXD0/MPIO
TXD0/MPIO
SCK1/MPIO
USART1
RXD1/MPIO
TXD1/MPIO
Capture0
Capture1
PWM
CAPT0
CAPT1
PWM[3:0]
Fast interrupt line
Hardware reset input
Master clock input
Master clock output
PLL RC network input
32.768 KHz clock input
32.768 KHz clock output
General purpose I/O
USART0 clock line
USART0 receive line
USART0 transmit line
USART1 clock line
USART1 receive line
USART1 transmit line
Capture input
Capture input
Pulse Width Modulation output
I
I
I
Connected to external crystal (4 to 6 Mhz)
O
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
I/O
I/O
I/O
(L)
(Z)
(Z)
(Z)
Multiplexed with a general purpose I/O
Multiplexed with a general purpose I/O
Multiplexed with a general purpose I/O
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Connected to external 32.768 Khz crystal
L
Schmitt input with internal filter
Function
External address bus
External address line line/
Lower byte enable
External address line/ Chip select
External data bus
Output enable
Write enable
Chip select lines
Upper byte enable
External Wait
Core CLock
External interrupt lines
Type
O
O
O
I/O
O
O
O
O
I
O
I
Active
Level Comments
(Z)
(1)
L (Z)
H (Z)
(Z)
L (Z)
L (Z)
L (Z)
L (Z)
L
Disable at reset, multiplexed with UPIO30
Disable at reset, multiplexed with UPIO31
The EBI is tri-stated when NRESET is at a
logical low level.
Internal pull-downs on data bus bits
T0TIOA[2:0]/MPIO Capture/waveform I/O
Timer T0
T0TIOB[2:0]/MPIO Trigger/waveform I/O
T0TIOCLK[2:0]/MP External clock/trigger/input
IO
PRELIMINARY
6021BS–ATARM–07/04
5
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