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BF998WR-T

TRANSISTOR 2 CHANNEL, UHF BAND, Si, N-CHANNEL, RF SMALL SIGNAL, MOSFET, MICRO MINIATURE, PLASTIC PACKAGE-4, FET RF Small Signal

器件类别:分立半导体    晶体管   

厂商名称:NXP(恩智浦)

厂商官网:https://www.nxp.com

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器件参数
参数名称
属性值
包装说明
SMALL OUTLINE, R-PDSO-G4
针数
4
Reach Compliance Code
unknown
ECCN代码
EAR99
其他特性
LOW NOISE
外壳连接
SOURCE
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
12 V
最大漏极电流 (ID)
0.03 A
FET 技术
METAL-OXIDE SEMICONDUCTOR
最高频带
ULTRA HIGH FREQUENCY BAND
JESD-30 代码
R-PDSO-G4
元件数量
2
端子数量
4
工作模式
DUAL GATE, DEPLETION MODE
最高工作温度
150 °C
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
极性/信道类型
N-CHANNEL
认证状态
Not Qualified
表面贴装
YES
端子形式
GULL WING
端子位置
DUAL
晶体管应用
AMPLIFIER
晶体管元件材料
SILICON
Base Number Matches
1
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DISCRETE SEMICONDUCTORS
DATA SHEET
BF998WR
N-channel dual-gate MOS-FET
Product specification
Supersedes data of 1995 Apr 25
1997 Sep 05
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
FEATURES
High forward transfer admittance
Short channel transistor with high forward transfer
admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz.
APPLICATIONS
VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipment.
DESCRIPTION
Depletion type field-effect transistor in a plastic
microminiature SOT343R package with source and
substrate interconnected. The transistor is protected
against excessive input voltage surges by integrated
back-to-back diodes between gates and source.
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
Marking code:
MB.
BF998WR
PINNING
PIN
1
2
3
4
SYMBOL
s, b
d
g
2
g
1
source
drain
gate 2
gate 1
DESCRIPTION
d
3
4
g
2
g1
2
1
s,b
Top view
MAM198
Fig.1 Simplified outline (SOT343R) and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
y
fs
C
ig1-s
C
rs
F
drain current
total power dissipation
operating junction temperature
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
f = 1 MHz
f = 800 MHz
PARAMETER
drain-source voltage
CONDITIONS
MIN.
24
2.1
25
1
TYP.
MAX.
12
30
300
150
UNIT
V
mA
mW
C
mS
pF
fF
dB
1997 Sep 05
2
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. Device mounted on a printed-circuit board.
PARAMETER
drain-source voltage
drain current
gate 1 current
gate 2 current
total power dissipation
storage temperature
operating junction temperature
up to T
amb
= 45
C;
see Fig.2; note 1
CONDITIONS
65
MIN.
BF998WR
MAX.
12
30
10
10
300
+150
+150
V
UNIT
mA
mA
mA
mW
C
C
MLD154
handbook, halfpage
400
Ptot
(mW)
300
200
100
0
0
50
100
150
200
o
Tamb ( C)
Fig.2 Power derating curve.
1997 Sep 05
3
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
R
th j-s
Notes
1. Device mounted on a printed-circuit board.
2. T
s
is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
T
j
= 25
C;
unless otherwise specified.
SYMBOL
V
(BR)G1-SS
V
(BR)G2-SS
V
(P)G1-S
V
(P)G2-S
I
DSS
I
G1-SS
I
G2-SS
PARAMETER
gate 1-source breakdown voltage
gate 2-source breakdown voltage
gate 1-source cut-off voltage
gate 2-source cut-off voltage
drain-source current
gate 1 cut-off current
gate 2 cut-off current
CONDITIONS
V
G2-S
= V
DS
= 0; I
G1-S
= 10 mA
V
G1-S
= V
DS
= 0; I
G2-S
= 10 mA
V
G2-S
= 4 V; V
DS
= 8 V; I
D
= 20
A
V
G1-S
= 0; V
DS
= 8 V; I
D
= 20
A
V
G2-S
= 4 V; V
DS
= 8 V; V
G1-S
= 0
V
G2-S
= V
DS
= 0; V
G1-S
= 5 V
V
G1-S
= V
DS
= 0; V
G2-S
= 5 V
MIN.
6
6
2
PARAMETER
thermal resistance from junction to ambient
thermal resistance from junction to soldering point
CONDITIONS
note 1
note 2; T
s
= 90
C
BF998WR
VALUE
350
200
UNIT
K/W
K/W
MAX.
20
20
2.5
2
18
50
50
UNIT
V
V
V
V
mA
nA
nA
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C;
V
G2-S
= 4 V; I
D
= 10 mA; V
DS
= 8 V; unless otherwise specified.
SYMBOL
y
fs
C
ig1-s
C
ig2-s
C
os
C
rs
F
PARAMETER
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
drain-source capacitance
noise figure
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 200 MHz; G
S
= 2 mS; B
S
= B
Sopt
CONDITIONS
pulsed; T
j
= 25
C
MIN.
22
TYP.
25
2.1
1.2
1.05
25
0.6
1
MAX.
2.5
UNIT
mS
pF
pF
pF
fF
dB
dB
reverse transfer capacitance f = 1 MHz
f = 800 MHz; G
S
= 3.3 mS; B
S
= B
Sopt
1997 Sep 05
4
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
MGC471
MGC470
24
3V
ID
(mA)
16
V G2 S = 4 V
2V
24
ID
(mA)
0.3 V
1V
16
0.2 V
0.1 V
0V
V G1 S =
0.4 V
8
8
−0.1
V
−0.2
V
0V
0
1
0
V G1 S (V)
1
0
0
2
4
6
8
−0.3
V
−0.4
V
−0.5
V
10
V DS (V)
V
DS
= 8 V.
T
amb
= 25
C.
V
G2-S
= 4 V.
T
amb
= 25
C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MGC472
MGC473
24
y fs
ID
(mS)
16
max
typ
30
(mS)
24
4V
3V
2V
1V
18
min
8
12
6
V G2
S = 0 V
0
−1600
−1200
−800
−400
0
0
400
VG1 (mV)
0
4
8
12
16
0.5 V
20
I D (mA)
V
DS
= 8 V; V
G2
= 4 V; T
amb
= 25
C.
V
DS
= 8 V; T
amb
= 25
C.
Fig.5
Drain current as a function of gate 1 voltage;
typical values.
Fig.6
Forward transfer admittance as a function
of drain current; typical values.
1997 Sep 05
5
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