BSI
n
FEATURES
Ultra Low Power/High Speed CMOS SRAM
256K X 16 bit
Ÿ
Ÿ
Ÿ
Ÿ
BS616UV4016
Ÿ
Wide V
CC
operation voltage :
C-grade : 1.8V ~ 3.6V
I-grade : 1.9V ~ 3.6V
(V
CC
_min.=1.65V at 25
O
C)
Ÿ
Ultra low power consumption :
V
CC
= 2.0V
C-grade : 10mA(Max.) operating current
I-grade : 12mA(Max.) operating current
0.3uA (Typ.) CMOS standby current
V
CC
= 3.0V
C-grade : 13mA(Max.) operating current
I-grade : 15mA(Max.) operating current
0.45uA (Typ.) CMOS standby current
Ÿ
High speed access time :
-85
85ns (Max.)
-10
100ns (Max.)
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin.
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.2V
n
DESCRIPTION
The BS616UV4016 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates form a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical CMOS standby current of
0.3uA at 2.0V/25
O
C and maximum access time of 85ns at 85
O
C.
Easy memory expansion is provided by an active LOW chip enable (CE)
and active LOW output enable (OE) and three-state output drivers.
The BS616UV4016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV4016 is available in DICE form, JEDEC standard 44-pin
TSOP Type II and 48-ball BGA package.
n
PRODUCT FAMILY
PRODUCT
FAMILY
BS616UV4016DC
BS616UV4016EC
BS616UV4016AC
BS616UV4016DI
BS616UV4016EI
BS616UV4016AI
-40
O
C to +85
O
C
1.9V ~ 3.6V
85/100
8.0uA
5.0uA
15mA
12mA
+0
O
C to +70
O
C
1.8V ~ 3.6V
85/100
6.0uA
3.0uA
13mA
10mA
OPERATING
TEMPERATURE
V
CC
RANGE
SPEED
(ns)
C-grade : 1.8~3.6V
I-grade : 1.9~3.6V
POWER DISSIPATION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.0V V
CC
=2.0V V
CC
=3.0V V
CC
=2.0V
DICE
TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608
n
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
GND
IO4
IO5
IO6
IO7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
IO15
IO14
IO13
IO12
GND
VCC
IO11
IO10
IO9
IO8
NC
A8
A9
A10
A11
A12
n
BLOCK DIAGRAM
BS616UV4016EC
BS616UV4016EI
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 4096
2048
IO0
.
.
.
.
.
.
IO15
.
.
.
.
.
.
16
Data
Input
Buffer
Data
Output
Buffer
16
256
Column Decoder
8
Control
Address Input Buffer
16
Column I/O
Write Driver
Sense Amp
1
A
B
C
D
E
F
G
H
UB
IO8
IO9
VSS
VCC
IO14
IO15
NC
2
OE
LB
IO10
IO11
IO12
IO13
NC
A8
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
IO1
IO3
IO4
IO5
WE
A11
6
NC
IO0
IO2
VCC
VSS
IO6
IO7
NC
16
CE
WE
OE
UB
LB
V
CC
GND
A13 A14 A15 A16 A17 A0 A1 A2
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to modify document contents without notice.
R0201-BS616UV4016
1
Revision 1.3
Sep.
2005
BSI
n
PIN DESCRIPTIONS
BS616UV4016
Function
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM
Name
A0-A17 Address Input
CE Chip Enable 1 Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If either chip enable is not active, the device is deselected and is in standby
power mode. The IO pins will be in the high impedance state when the device is
deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the IO
pins; when WE is LOW, the data present on the IO pins will be written into the selected
memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the IO pins and they
will be enabled. The IO pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
IO0-IO15 Data Input/Output
Ports
V
CC
GND
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n
TRUTH TABLE
MODE
Chip De-selected
(Power Down)
CE
H
X
L
WE
X
X
H
H
OE
X
X
H
H
LB
X
H
L
X
L
UB
X
H
X
L
L
L
H
L
L
H
IO0~IO7
High Z
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
X
D
IN
IO8~IO15
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
Output Disabled
L
Read
L
H
L
H
L
L
Write
L
L
X
H
L
NOTES: H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
R0201-BS616UV4016
2
Revision 1.3
Sep.
2005
BSI
n
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
BS616UV4016
n
OPERATING RANGE
UNITS
V
O
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
to 4.6V
-40 to +85
-60 to +150
1.0
20
RANG
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to + 70
O
C
-40
O
C to + 85
O
C
Vcc
1.8V ~ 3.6V
1.9V ~ 3.6V
C
C
W
MA
n
CAPACITANCE
(1)
(T
A
= 25 C, f = 1.0MHz)
O
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
2.
–2.0V
in case of AC pulse width less than 30 ns
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
n
DC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
I
CCSB
I
CCSB1
(5)
O
O
PARAMETER
Power Supply
TEST CONDITIONS
MIN.
1.9
V
CC
=2.0V
V
CC
=3.0V
TYP.
(1)
--
MAX.
3.6
0.6
0.8
UNITS
V
Input Low Voltage
-0.3
(2)
1.4
2.0
--
--
V
Input High Voltage
V
IN
= 0V to V
CC
,
CE = V
IH
V
I/O
= 0V to V
CC
CE= V
IH
, or OE = V
IH
V
CC
= Max, I
OL
= 0.1mA
V
CC
= Max, I
OL
= 2.0mA
Output High Voltage
Operating
Current
Power
Supply
V
CC
= Min, I
OH
= -0.1mA
V
CC
= Min, I
OH
= -1.0mA
CE = V
IL
,
I
IO
= 0mA, f = F
MAX(4)
CE = V
IH
,
I
IO
= 0mA
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=2.0V
V
CC
=3.0V
--
V
CC
+0.3
(3)
V
Input Leakage Current
--
1
uA
Output Leakage Current
--
V
CC
=2.0V
V
CC
=3.0V
V
CC
=2.0V
V
CC
=3.0V
V
CC
=2.0V
V
CC
=3.0V
V
CC
=2.0V
V
CC
=3.0V
V
CC
=2.0V
V
CC
=3.0V
--
1
0.2
0.4
uA
Output Low Voltage
--
V
CC
-0.2
2.4
--
--
V
--
--
12
15
V
--
mA
Standby Current
–
TTL
--
--
0.3
0.45
0.5
1.0
mA
Standby Current
–
CMOS
--
5.0
8.0
uA
1. Typical characteristics are at T
A
=25
O
C.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
5. I
CCSB1(MAX)
is 3.0/6.0uA at V
CC
=2.0V/3.0V and T
A
=70
O
C.
R0201-BS616UV4016
3
Revision 1.3
Sep.
2005
BSI
n
DATA RETENTION CHARACTERISTICS (T
A
= -40 C to +85 C)
SYMBOL
V
DR
I
CCDR
(3)
BS616UV4016
O
O
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN.
1.2
--
0
TYP.
(1)
--
0.15
--
--
MAX.
--
1.7
--
--
UNITS
V
uA
ns
ns
t
CDR
t
R
See Retention Waveform
t
RC (2)
1. V
CC
=1.2V, T
A
=25
O
C.
2. t
RC
= Read Cycle Time.
3. I
CCRD_Max.
is 1.2uA at T
A
=70
O
C.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
DR
≧1.0V
V
CC
V
IH
V
CC
V
CC
t
CDR
CE≧V
CC
- 0.2V
t
R
V
IH
CE
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BS616UV4016
4
Revision 1.3
Sep.
2005
BSI
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Data Byte Control to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
(CE)
(LB, UB)
(CE)
(LB, UB)
(CE)
(LB, UB)
CYCLE TIME : 85ns
(V
CC
=1.9~3.6V)
MIN. TYP. MAX.
85
--
--
--
--
15
15
15
--
--
--
15
--
--
--
--
--
--
--
--
--
--
--
--
--
85
85
40
40
--
--
--
35
35
35
--
O
O
BS616UV4016
CYCLE TIME : 100ns
(V
CC
=1.9~3.6V)
MIN. TYP. MAX.
100
--
--
--
--
15
15
15
--
--
--
15
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
50
50
--
--
--
40
40
40
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQX
t
ELQV
t
BLQV
t
GLQV
t
ELQX
t
BLQX
t
GLQX
t
EHQZ
t
BHQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS
t
BA
(1)
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
NOTE :
1. t
BA
is 40ns/50ns(@speed=85ns/100ns) with address toggle; t
BA
is 85ns/100ns(@speed=85ns/100ns) without address toggle
n
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
READ CYCLE 2
CE
(1,3,4)
t
ACS
t
BA
LB, UB
t
BE
D
OUT
t
CLZ
(5)
t
CHZ
t
BDO
(5)
R0201-BS616UV4016
5
Revision 1.3
Sep.
2005
