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DISCRETE SEMICONDUCTORS
DATA SHEET
BSP230
P-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of 1997 Jun 17
File under Discrete Semiconductors, SC13b
1997 Oct 21
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
FEATURES
•
Direct interface to C-MOS, TTL, etc.
•
High-speed switching
•
No secondary breakdown.
APPLICATIONS
•
Line current interruptor in telephone sets
•
Relay, high speed and line transformer drivers.
1
Top view
2
3
MAM121
BSP230
handbook, halfpage
4
d
g
s
DESCRIPTION
P-channel enhancement mode vertical D-MOS transistor
in a SOT223 plastic SMD package.
PINNING - SOT223
PIN
1
2
3
4
SYMBOL
g
d
s
d
DESCRIPTION
gate
drain
source
drain
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
V
GSO
V
GSth
I
D
R
DSon
P
tot
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
gate-source threshold voltage
drain current (DC)
drain-source on-state resistance
total power dissipation
I
D
=
−170
mA; V
GS
=
−10
V
T
amb
≤
25
°C
open drain
I
D
=
−1
mA; V
DS
= V
GS
CONDITIONS
−
−
−1.95
−
−
−
MIN.
MAX.
−300
±20
−2.8
−210
17
1.5
V
V
V
mA
Ω
W
UNIT
1997 Oct 21
2
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
operating junction temperature
T
amb
≤
25
°C;
note 1
open drain
CONDITIONS
−
−
−
−
−
−65
−
MIN.
BSP230
MAX.
−300
±20
−210
−0.75
1.5
+150
150
V
V
UNIT
mA
A
W
°C
°C
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
PARAMETER
thermal resistance from junction to ambient
CONDITIONS
note 1
VALUE
83.3
UNIT
K/W
Note to the Limiting values and Thermal characteristics
1. Device mounted on an epoxy printed-circuit board, 40
×
40
×
1.5 mm; mounting pad for drain lead minimum 6 cm
2
.
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
y
fs
C
iss
C
oss
C
rss
t
on
t
off
PARAMETER
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
gate leakage current
drain-source on-state resistance
forward transfer admittance
input capacitance
output capacitance
reverse transfer capacitance
CONDITIONS
V
GS
= 0; I
D
=
−10 µA
V
DS
= V
GS
; I
D
=
−1
mA
V
GS
= 0; V
DS
=
−240
V
V
GS
=
±20
V; V
DS
= 0
V
GS
=
−10
V; I
D
=
−170
mA
V
DS
=
−25
V; I
D
=
−170
mA
MIN.
−300
−1.95
−
−
−
100
TYP.
−
−
−
−
−
−
60
15
5
MAX.
−
−2.8
−100
±100
17
−
90
30
15
UNIT
V
V
nA
nA
Ω
mS
pF
pF
pF
V
GS
= 0; V
DS
=
−25
V; f = 1 MHz
−
V
GS
= 0; V
DS
=
−25
V; f = 1 MHz
−
V
GS
= 0; V
DS
=
−25
V; f = 1 MHz
−
V
GS
= 0 to
−10
V; V
DD
=
−50
V;
I
D
=
−250
mA
V
GS
=
−10
to 0 V; V
DD
=
−50
V;
I
D
=
−250
mA
−
−
Switching times
(see Figs 2 and 3)
turn-on time
turn-off time
5
15
10
30
ns
ns
1997 Oct 21
3
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSP230
handbook, halfpage
VDD =
−50
V
handbook, halfpage
10 %
INPUT
90 %
0V
−10
V
ID
50
Ω
10 %
OUTPUT
90 %
MBB689
ton
toff
MBB690
Fig.2 Switching time test circuit.
Fig.3 Input and output waveforms.
handbook, halfpage
1.6
MLC687
handbook, halfpage
−1
MLC694
Ptot
(W)
1.2
tp =
(1)
10
µs
100
µs
1 ms
10 ms
100 ms
tp
T
DC
tp
t
T
−10
−10
2
VDS (V)
−10
3
1s
ID
(A)
−10
−1
0.8
−10
−2
0.4
P
δ
=
0
0
50
100
150
200
Tamb (°C)
−10
−3
−1
δ
= 0.01.
T
amb
= 25
°C.
(1) R
DSon
limitation.
Fig.4 Power derating curve.
Fig.5 DC SOAR.
1997 Oct 21
4
