Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope using ’trench’
technology. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection up to 2kV. It is intended for
use in automotive and general
purpose switching applications.
BUK9518-30
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 5 V
MAX.
30
55
103
175
18
UNIT
V
A
W
˚C
mΩ
PINNING - TO220AB
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
10
55
38
220
103
175
UNIT
V
V
V
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
in free air
TYP.
-
60
MAX.
1.45
-
UNIT
K/W
K/W
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
December 1997
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
(BR)GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
Gate-source breakdown
voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 30 V; V
GS
= 0 V;
V
GS
=
±5
V; V
DS
= 0 V
I
G
=
±1
mA;
V
GS
= 5 V; I
D
= 25 A
T
j
= 175˚C
T
j
= 175˚C
T
j
= 175˚C
MIN.
30
27
1
0.5
-
-
-
-
-
10
-
-
TYP.
-
-
1.5
-
-
0.05
-
0.02
-
15
-
BUK9518-30
MAX.
-
-
2
-
2.3
10
500
1
10
-
18
34
UNIT
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
g
fs
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
PARAMETER
Forward transconductance
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
CONDITIONS
V
DS
= 25 V; I
D
= 25 A
I
D
= 55 A; V
DD
= 24 V; V
GS
= 5 V
MIN.
10
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP.
20
31
4
13
1450
390
200
30
80
95
40
3.5
4.5
7.5
MAX.
-
-
-
-
-
-
-
45
130
135
55
-
-
-
UNIT
S
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
nH
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
V
DD
= 15 V; I
D
= 25 A;
V
GS
= 5 V; R
G
= 5
Ω
Resistive load
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
December 1997
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 55 A; V
GS
= 0 V
I
F
= 55 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 25 V
-
-
-
-
-
TYP.
-
-
0.95
1.0
70
0.1
BUK9518-30
MAX.
55
220
1.2
-
-
-
UNIT
A
A
V
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 28 A; V
DD
≤
25 V;
V
GS
= 10 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
TYP.
-
MAX.
80
UNIT
mJ
December 1997
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
BUK9518-30
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1E+01
Zth / (K/W)
1E+00
0.5
0.2
0.1
0.05
0.02
0
T
t
1E-01
P
D
t
p
p
D= t
T
1E-02
0
20
40
60
80 100
Tmb / C
120
140
160
180
1E-03
1E-07
1E-05
1E-03
t/s
1E-01
1E+01
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
ID%
Normalised Current Derating
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
ID / A
10
8
60
3.5
40
VGS / V =
20
2.5
2
0
3
6
BUK9518-30
4
120
110
100
90
80
70
60
50
40
30
20
10
0
80
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
2
4
VDS / V
6
8
10
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON) / mOhm
3.5
4
1000
ID / A
7518-30
40
9518-30
100
RD
S
)
(ON
DS
=V
/ ID
tp = 10 us
100 us
30
6
20
8
10
VGS / V =
10
1 ms
10
DC
10 ms
100 ms
1
1
10
VDS / V
100
0
0
20
40
ID / A
60
80
100
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
December 1997
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
BUK9518-30
80
ID / A
9518-30
2.5
VGS(TO) / V
max.
BUK959-60
Tj / C = 25
60
175
2
typ.
1.5
40
1
min.
20
0.5
0
0
1
2
3
VGS / V
4
5
6
0
-100
-50
0
50
Tj / C
100
150
200
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
gfs / S
9518-30
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
40
1E-01
30
Tj / C = 25
175
20
1E-02
2%
typ
98%
1E-03
1E-04
10
1E-05
0
0
20
40
ID / A
60
80
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
a
2
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
C / pF
30V TrenchMOS
10000
9518-30
1.5
Ciss
1
1000
0.5
Coss
Crss
0
-100
-50
0
50
Tj / C
100
150
200
100
0.1
1
VDS / V
10
100
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
December 1997
5
Rev 1.100
