CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
D
D
D
D
D
D
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA
Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
CD54AC00 . . . F PACKAGE
CD74AC00 . . . E OR M PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
description
The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A
S
B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
PACKAGE†
PDIP – E
–55°C to 125°C
55°C
SOIC – M
CDIP – F
Tube
Tube
Tape and reel
Tube
ORDERABLE
PART NUMBER
CD74AC00E
CD74AC00M
CD74AC00M96
CD54AC00F3A
TOP-SIDE
MARKING
CD74AC00E
AC00M
CD54AC00F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
logic diagram, each gate (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±100
mA
Package thermal impedance,
θ
JA
(see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
MIN
VCC
Supply voltage
VCC = 1.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 1.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
0
0
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 1.5 V to 3 V
VCC = 3.6 V to 5.5 V
1.5
1.2
2.1
3.15
3.85
0.3
0.9
1.35
1.65
VCC
VCC
–24
24
50
20
0
0
1.65
VCC
VCC
–24
24
50
20
0
0
3.85
0.3
0.9
MAX
5.5
–40°C TO
85°C
MIN
1.5
1.2
2.1
MAX
5.5
–55°C TO
125°C
MIN
1.5
1.2
2.1
3.15
3.85
0.3
0.9
1.35
1.65
VCC
VCC
–24
24
50
20
V
V
mA
mA
ns/V
V
V
MAX
5.5
V
UNIT
VIH
High-level
High level input voltage
VIL
Low-level
Low level input voltage
VI
VO
IOH
IOL
∆t/∆v
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
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DALLAS, TEXAS 75265
CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.5 V
IOH = –50
µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –24 mA
IOH = –50 mA†
IOH = –75 mA†
IOL = 50
µA
VOL
VI = VIH or VIL
IOL = 12 mA
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
II
ICC
Ci
VI = VCC or GND
VI = VCC or GND,
IO = 0
3V
4.5 V
3V
4.5 V
5.5 V
5.5 V
1.5 V
3V
4.5 V
3V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
±0.1
4
10
1.65
±1
40
10
±1
80
10
µA
µA
pF
0.1
0.1
0.1
0.36
0.36
3.85
0.1
0.1
0.1
0.44
0.44
0.1
0.1
0.1
0.5
0.5
1.65
V
TA = 25°C
MIN
1.4
2.9
4.4
2.58
3.94
MAX
–40°C TO
85°C
MIN
1.4
2.9
4.4
2.48
3.8
MAX
–55°C TO
125°C
MIN
1.4
2.9
4.4
2.4
3.7
3.85
V
MAX
UNIT
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 1.5 V, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
–40°C TO
85°C
MIN
MAX
83
83
–55°C TO
125°C
MIN
MAX
91
91
ns
UNIT
A or B
Y
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
–40°C TO
85°C
MIN
A or B
Y
2.7
2.7
MAX
9.3
9.3
–55°C TO
125°C
MIN
2.6
2.6
MAX
10.2
10.2
ns
UNIT
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CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
–40°C TO
85°C
MIN
1.9
1.9
MAX
6.6
6.6
–55°C TO
125°C
MIN
1.8
1.8
MAX
7.3
7.3
ns
UNIT
A or B
Y
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TYP
45
UNIT
pF
4
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CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
R1 = 500
Ω
†
S1
2
×
VCC
Open
GND
R2 = 500
Ω
†
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
×
VCC
GND
From Output
Under Test
CL = 50 pF
(see Note A)
tw
† When VCC = 1.5 V, R1 = R2 = 1 kΩ
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
0V
tsu
Data
50%
Input 10%
90%
tr
th
90%
VCC
50% VCC
10% 0 V
tf
VCC
Input
50% VCC
50% VCC
0V
CLR
Input
VCC
50% VCC
0V
trec
VCC
Reference
Input
CLK
50% VCC
0V
VOLTAGE WAVEFORMS
RECOVERY TIME
VCC
50% VCC
tPLH
50% VCC
0V
tPHL
90%
tr
tPHL
tPLH
50% VCC
10%
tf
50%
10%
V
90% OH
tr
VOL
90%
VOH
50% VCC
10%
VOL
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
Output
Control
tPZL
VCC
50% VCC
50% VCC
0V
tPLZ
≈V
CC
50% VCC
tPZH
20% VCC
VOL
tPHZ
50% VCC
VOH
80% VCC
≈0
V
In-Phase
Output
50%
10%
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
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