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Cicada

Semiconductor Corporation

CIS8201 Data Sheet

SimpliPHY

™

Gigabit Ethernet PHY Series

CIS8201

Single Port, Low Power, 10 / 100 / 1000BASE-T PHYwith GMII / MII, RGMII, TBI and RTBI MAC Interfaces

1 General Description

Enabling widespread, low-cost, Gigabit-to-the-Desktop

deployment, Cicada's low-power, single chip CIS8201

integrates a complete triple speed (10BASE-T, 100BASE-

TX, and 1000BASE-T) Ethernet physical layer transceiver in

two small footprint package options. RJ-45 footprint

compatible options are a 128-pin Plastic Low-Profile Quad

Flat Pack (LQFP) package, and a 11x11mm footprint 100-

ball LBGA package.

The 1000BASE-T transceiver features the industry standard

GMII/MII, plus the pin-saving RGMII / RTBI system

interfaces. Unlike competitors’ products, the CIS8201

integrates self-calibrating series termination resistors on

MAC interface pins, simplifying system design significantly

by eliminating more than a dozen external components.

These innovative terminations also reduce PCB layout

complexity, increase system timing margins, and minimize

EMI engineering challenges. In addition, the CIS8201

includes innovative on-chip RGMII timing compensation

circuits on the MAC interface pins to simplify PCB design.

The twisted pair interface includes an innovative internal

hybrid and a very low EMI line driver with robust Cable

Sourced ESD (CESD) performance, allowing the use of the

lowest-cost 1:1 magnetic modules, minimum external

components, and less complex PCB traces. To further

reduce system complexity and cost, the CIS8201 can

optionally be powered from a single 3.3V power supply

when utilizing the device's on-chip regulator control circuit to

produce the 1.5V core power supply voltage.

The CIS8201 leverages Cicada's proprietary

2nd

generation SimpliPHY™ DSP Technology,

key to

enabling an extremely low-power Gigabit PHY on a single

chip. Cicada's mixed signal and DSP architecture yields

robust performance, supporting both full- and half-duplex

10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet over

unshielded twisted pair (UTP) cable, with more than 5dB of

design margin with respect to all worst-case impairments

(NEXT, FEXT, Echo, and system noise). The industry's

highest-performance, low-power DSP-based transceiver

utilizes an optimum trellis decoding algorithm in concert with

all digital gain control and timing recovery.

To enable maximum network management feedback to the

host system and the user, Cicada-provided software

routines, referred to as the VeriPHY

Link Management

Suite, allow extensive network and cable plant operating

and status information, such as the cable length and the

effective Bit Error Rate (BER), to be easily integrated with

NIC or switch software, greatly simplifying Gigabit Ethernet

network deployment and management.

2 System Diagram

128-pin LQFP (14mm x 20mm)

100-ball LBGA (11mm x 11mm)

GMII / MII

RGMII

TBI

RTBI

10/100/1000

NIC Controller,

Switching ASIC

Network Processor

CIS8201

10/100/1000BASE-T

Transceiver

Quad

Transformer

Module

RJ-45

Connector

4-Pair

UTP-5

Cable

Management I/F (MDC / MDIO)

25MHz

Figure 2-1. CIS8201 System Diagram

Rev. 1.2.2 - 12 Sep 2003

- Page 1 of 136 -

CIS8201 Data Sheet

3 Features

•

<1.0W power consumption

Optional on-chip regulator control circuit

Advanced Power Management complies with PC99/

PC2000, Wake on LAN

, & PCI 2.2 power

requirements

Fully IEEE 802.3, 802.3u (10BASE-T, 100BASE-TX), &

802.3ab (1000BASE-T) compliant

Automatic detection & correction of cable pair swaps,

pair skew, & pair polarity, along with an Auto MDI/MDI-X

crossover function

Choice of standard GMII/MII or TBI, or pin-saving

RGMII/RTBI interfaces

Self-calibrating, series termination resistors on MAC

interface pins

Unique on-chip RGMII timing compensation supports

both 2.5V and 3.3V RGMII operation

Optional integrated oscillator circuit

>10KB jumbo frame support with programmable

synchronization FIFOs

Six direct drive LED pins

Low EMI line drivers with robust CESD performance

Manufactured in mainstream, 3.3V/1.5V digital CMOS

process

Choice of two small footprint packages:

- 14x20mm LQFP

- 11x11mm LBGA

•

Benefits

Eliminates expensive regulators, heat sinks & fans

Enables a single 3.3V supply design for lowest cost

Enables widespread, low-cost, 1000BASE-T

deployment in desktop LOM, NICs, & switches

Ensures full specification compliance & seamless

deployment throughout Category-5 networks with the

industry’s highest performance & noise immunity

Compatible with first generation 1000BASE-T PHYs,

allowing trouble-free migration to 1000BASE-T by

minimizing common interoperability problems

Connects to existing GMII and TBI-based MACs, or

significantly reduces pin-count requirements on MAC &

switching ASICs from 24 (GMII) to 12 (RGMII).

Eases board designs & EMI challenges, improves MAC

I/F signal integrity, lowers power consumption, &

eliminates >12 external components on a system board

Decreases board design efforts, increases PCB timing

margins & yields, & shortens time to market

Supports single low-cost 25MHz crystal, or either a

25MHz or 125MHz standard reference clock input

Provides for maximum jumbo frame sizes in custom

SAN & LAN systems

LED flexibility with minimum external components

Reduces EMI & qualification engineering risks & efforts

Minimizes costs & enables highest PHY integration

levels & process portability

Low cost plastic packaging compatible with compact PC

LAN-on-Motherboards

•

4 Applications

•

Desktop and Server NICs

LAN-on-Motherboard and Mobile PC NICs

•

Workgroup and Desktop Switches/Routers

SAN Switches and NAS Appliances

Rev. 1.2.2 - 12 Sep 2003

- Page 2 of 136 -

CIS8201 Data Sheet

5 Device Block Diagram

MAC I/F

PCS

PMA (DSP Data Pump)

MDI (Analog Front End)

TXD[7:0]

GTX_CLK

TX_ER

TX_EN

TX_CLK

COL

CRS

PCS

ENCODER

GMII

MII

RGMII

TBI

PCS

DECODER

PAM-5 SYMBOL

DE-MAPPER,

DESCRAMBLER

PAM-5 SYMBOL

MAPPER,

SCRAMBLER

TX FIR

DAC

HYBRID

TXIP_A

TXVP_A

TXVN_A

TXIN_A

TXIP_B

TXVP_B

TXVN_B

TXIN_B

TXIP_C

TXVP_C

TXVN_C

TXIN_C

TXIP_D

TXVP_D

TXVN_D

TXIN_D

PLLMODE

XTAL2

XTAL1 / REFCLK

OSC_EN / CLK125

NC1

NC2

NC3

RXD[7:0]

RX_CLK

RX_DV

RX_ER

RST#

PWDN#

TDI

TDO

TMS

TCK

TRST#

MDC

MDIO

MDINT#

FRC_DPLX

ANEG_DIS

MODE10

MODE100

MODE1000

TRELLIS

DECODER

FFE

ADC

VGA

RTBI

TIMING RECOVERY

TEST

MANAGER

PLL,

OSCILLATOR

AUTO-NEGOTIATION

BIASING &

REGULATION

REF_FILT

REF_REXT

REG_EN / QUALITY

REG_OUT

ADDR(4) / ACTIVITY

SERIAL

MANAGEMENT

INTERFACE

MII

REGISTERS

LED

INTERFACE

ADDR(3) / DUPLEX

ADDR(2) / LINK1000

ADDR(1) / LINK100

ADDR(0) / LINK10

Figure 5-1. CIS8201 Block Diagram

Rev. 1.2.2 - 12 Sep 2003

- Page 3 of 136 -

CIS8201 Data Sheet

Table of Contents

ENERAL

ESCRIPTION

.............................................................................................................................................................1

YSTEM

IAGRAM

..................................................................................................................................................................... 1

EATURES

& B

ENEFITS

.............................................................................................................................................................2

PPLICATIONS

.......................................................................................................................................................................... 2

EVICE

LOCK

IAGRAM

.......................................................................................................................................................... 3

ELEVANT

PECIFICATIONS

& D

OCUMENTATION

...................................................................................................................... 11

ATA

HEET

ONVENTIONS

.................................................................................................................................................... 12

UNCTIONAL

VERVIEW

..........................................................................................................................................................13

8.1

MAC I

NTERFACE

(GMII / RGMII / MII,

TBI / RTBI) .................................................................................................. 13

8.2

WISTED

AIR

NTERFACE

(TPI) .................................................................................................................................... 13

8.3

ERIAL

ANAGEMENT

NTERFACE

(SMI) ........................................................................................................................ 14

8.4

ARALLEL

LED I

NTERFACE

(PLI) ................................................................................................................................... 14

8.5

YSTEM

LOCK

NTERFACE

(SCI).................................................................................................................................. 14

8.6

EST

ODE

NTERFACE

(TMI) .......................................................................................................................................14

8.7

NALOG

RONT

(AFE)........................................................................................................................................... 14

8.8

DSP D

ATA

UMP

ORE

................................................................................................................................................15

8.9

HYSICAL

ODING

UBLAYER

(PCS) .............................................................................................................................15

8.10 S

YNCHRONIZATION

FIFO

............................................................................................................................................. 16

8.11 O

PTIONAL

IXED

OWER

UPPLY

EGULATOR

............................................................................................................... 16

ACKAGE

SSIGNMENTS

& S

IGNAL

ESCRIPTIONS

............................................................................................................ 17

9.1

128 P

LQFP P

ACKAGE

INOUT

IAGRAM

...................................................................................................................17

9.2

100 B

ALL

LBGA P

ACKAGE

ALLOUT

IAGRAM

............................................................................................. 18

9.3

ESCRIPTIONS

........................................................................................................................................................ 19

9.4

IGNAL

YPE

ESCRIPTIONS

......................................................................................................................................... 19

9.5

MAC T

RANSMIT

NTERFACE

INS

(MAC TX)..................................................................................................................20

9.6

MAC R

ECEIVE

NTERFACE

INS

(MAC RX) ...................................................................................................................22

9.7

WISTED

AIR

NTERFACE

INS

(TPI) ........................................................................................................................... 25

9.8

ERIAL

ANAGEMENT

NTERFACE

INS

(SMI) ................................................................................................................ 27

9.9

ONFIGURATION AND

ONTROL

INS

ONFIG

).............................................................................................................. 27

9.10 S

YSTEM

LOCK

NTERFACE

INS

(SCI).......................................................................................................................... 29

9.11 P

ARALLEL

LED I

NTERFACE

INS

(PLI) ........................................................................................................................... 29

9.12 JTAG T

EST

CCESS

ORT

(TAP) ................................................................................................................................. 30

9.13 R

EGULATOR

ONTROL AND

NALOG

IAS

INS

(AP)...................................................................................................... 30

9.14 N

ONNECTS

(NC) ..................................................................................................................................................... 31

9.15 D

IGITAL

OWER

UPPLY

INS FOR

LQFP P

ACKAGE

....................................................................................................... 31

9.16 D

IGITAL

OWER

UPPLY

INS FOR

LBGA P

ACKAGE

...................................................................................................... 31

9.17 A

NALOG

OWER

UPPLY

INS FOR

LQFP P

ACKAGE

...................................................................................................... 32

9.18 A

NALOG

OWER

UPPLY

INS FOR

LBGA P

ACKAGE

...................................................................................................... 32

10 S

YSTEM

CHEMATICS

.............................................................................................................................................................. 33

10.1 G

ENERAL

YSTEM

CHEMATIC

EPARATE

3.3V

AND

1.5V S

UPPLY

PPLICATION WITH

EGULATOR

ISABLED

) .............. 33

10.2 S

EPARATE

3.3V

AND

1.5V P

OWER

UPPLY

ONFIGURATION

.......................................................................................... 34

10.3 3.3V P

OWER

UPPLY WITH

PTIONAL

IXED

EGULATOR AT

1.5V ................................................................................. 35

10.4 PLI C

ONNECTIONS

........................................................................................................................................................ 36

11 MAC I

NTERFACES

................................................................................................................................................................... 37

11.1 GMII MAC I/F............................................................................................................................................................... 37

11.2 MII MAC I/F ................................................................................................................................................................. 38

11.3 RGMII MAC I/F ............................................................................................................................................................ 39

11.4 TBI MAC I/F................................................................................................................................................................. 40

11.5 RTBI MAC I/F .............................................................................................................................................................. 41

12 S

ERIAL

ANAGEMENT

NTERFACE

(SMI) ................................................................................................................................. 42

12.1 SMI I

NTERRUPT

............................................................................................................................................................ 43

13 P

ARALLEL

LED I

NTERFACE

..................................................................................................................................................... 44

14 T

EST

ODE

NTERFACE

(JTAG).............................................................................................................................................. 45

14.1 S

UPPORTED

NSTRUCTIONS AND

NSTRUCTION

ODES

.................................................................................................... 46

14.2 B

OUNDARY

-S

CAN

EGISTER

ELL

RDER

..................................................................................................................... 47

14.3 NAND T

REE

EST

ODE

.............................................................................................................................................. 49

Rev. 1.2.2 - 12 Sep 2003

- Page 4 of 136 -

CIS8201 Data Sheet

15 I

NITIALIZATION

& C

ONFIGURATION

........................................................................................................................................... 50

15.1 R

ESETS

........................................................................................................................................................................ 50

15.2 P

OWER

-U

EQUENCE

.................................................................................................................................................. 50

15.3 M

ANUAL

ONFIGURATION

.............................................................................................................................................. 51

15.4 A

UTO

-N

EGOTIATION

...................................................................................................................................................... 51

15.5 MAC I/F C

ONFIGURATION

.............................................................................................................................................. 52

15.6 S

YSTEM

LOCK

NTERFACE

(SCI).................................................................................................................................. 52

15.7 A

UTO

MDI / MDI-X F

UNCTION

.......................................................................................................................................53

15.8 P

ARALLEL

LED I/F ........................................................................................................................................................ 54

15.9 A

CTI

PHYTM P

OWER

ANAGEMENT

.............................................................................................................................. 54

15.10 P

OWER

UPPLY

ECOUPLING AND

OARD

AYOUT

UIDELINES

.....................................................................................54

16 MII R

EGISTER

ONVENTIONS

........................................................................................................................................... 55

16.1 MII R

EGISTER

AMES

& A

DDRESSES

.............................................................................................................................55

16.2 R

ESET

-S

TICKY

ITS

...................................................................................................................................................... 56

16.3 MII R

EGISTER

UICK

EFERENCE

HEET

2) ................................................................................................. 57

16.4 MII R

EGISTER

UICK

EFERENCE

HEET

2) ................................................................................................. 58

17 MII R

EGISTER

ESCRIPTIONS

.................................................................................................................................................. 59

17.1 R

EGISTER

0 (00

) – M

ODE

ONTROL

EGISTER

............................................................................................................ 59

17.2 R

EGISTER

1 (01

) – M

ODE

TATUS

EGISTER

.............................................................................................................. 61

17.3 R

EGISTER

2 (02

) – PHY I

DENTIFIER

EGISTER

#1 ....................................................................................................... 63

17.4 R

EGISTER

3 (03

) – PHY I

DENTIFIER

EGISTER

#2 ....................................................................................................... 63

17.5 R

EGISTER

4 (04

) – A

UTO

-N

EGOTIATION

DVERTISEMENT

EGISTER

............................................................................. 64

17.6 R

EGISTER

5 (05

) – A

UTO

-N

EGOTIATION

INK

ARTNER

BILITY

EGISTER

................................................................... 65

17.7 R

EGISTER

6 (06

) – A

UTO

-N

EGOTIATION

XPANSION

EGISTER

.................................................................................... 66

17.8 R

EGISTER

7 (07

) – A

UTO

-N

EGOTIATION

EXT

-P

AGE

RANSMIT

EGISTER

.................................................................... 67

17.9 R

EGISTER

8 (08

) – A

UTO

-N

EGOTIATION

INK

ARTNER

EXT

-P

AGE

ECEIVE

EGISTER

..............................................68

17.10 R

EGISTER

9 (09

) – 1000BASE-T C

ONTROL

EGISTER

................................................................................................ 69

17.11 R

EGISTER

10 (0A

) – 1000BASE-T S

TATUS

EGISTER

................................................................................................ 71

17.12 R

EGISTER

11 (0B

) – R

ESERVED

EGISTER

..................................................................................................................73

17.13 R

EGISTER

12 (0C

) – R

ESERVED

EGISTER

..................................................................................................................73

17.14 R

EGISTER

13 (0D

) – R

ESERVED

EGISTER

..................................................................................................................73

17.15 R

EGISTER

14 (0E

) – R

ESERVED

EGISTER

..................................................................................................................73

17.16 R

EGISTER

15 (0F

) – 1000BASE-T S

TATUS

XTENSION

EGISTER

#1 ......................................................................... 74

17.17 R

EGISTER

16 (10

) – 100BASE-TX S

TATUS

XTENSION

EGISTER

.............................................................................. 75

17.18 R

EGISTER

17 (11

) – 1000BASE-T S

TATUS

XTENSION

EGISTER

#2.......................................................................... 77

17.19 R

EGISTER

18 (12

) – B

YPASS

ONTROL

EGISTER

....................................................................................................... 79

17.20 R

EGISTER

19 (13

) – R

ECEIVE

RROR

OUNTER

EGISTER

.......................................................................................... 82

17.21 R

EGISTER

20 (14

) – F

ALSE

ARRIER

ENSE

OUNTER

EGISTER

................................................................................ 82

17.22 R

EGISTER

21 (15

) – D

ISCONNECT

OUNTER

EGISTER

...............................................................................................82

17.23 R

EGISTER

22 (16

) – 10BASE-T C

ONTROL

& S

TATUS

EGISTER

.................................................................................. 83

17.24 R

EGISTER

23 (17

) – E

XTENDED

PHY C

ONTROL

EGISTER

#1 .....................................................................................85

17.25 R

EGISTER

24 (18

) – E

XTENDED

PHY C

ONTROL

EGISTER

#2 .....................................................................................87

17.26 R

EGISTER

25 (19

) – I

NTERRUPT

ASK

EGISTER

........................................................................................................89

17.27 R

EGISTER

26 (1A

) – I

NTERRUPT

TATUS

EGISTER

..................................................................................................... 91

17.28 R

EGISTER

27 (1B

) – P

ARALLEL

LED C

ONTROL

EGISTER

............................................................................................ 93

17.29 R

EGISTER

28 (1C

) – A

UXILIARY

ONTROL

& S

TATUS

EGISTER

................................................................................... 95

17.30 R

EGISTER

29 (1D

) – D

ELAY

KEW

TATUS

EGISTER

................................................................................................. 98

17.31 R

EGISTER

30 (1E

) – R

ESERVED

EGISTER

..................................................................................................................99

17.32 R

EGISTER

31 (1F

) – R

ESERVED

EGISTER

..................................................................................................................99

18 E

LECTRICAL

PECIFICATION

..................................................................................................................................................100

18.1 A

BSOLUTE

AXIMUM

ATINGS

.....................................................................................................................................100

18.2 R

ECOMMENDED

PERATING

ONDITIONS

.....................................................................................................................101

18.3 T

HERMAL

PPLICATION

ATA

.......................................................................................................................................102

18.4 T

HERMAL

PECIFICATIONS

...........................................................................................................................................102

18.5 C

URRENT AND

OWER

ONSUMPTION

- A

PPLICATION

CENARIOS

................................................................................103

18.6 C

RYSTAL

PECIFICATIONS

...........................................................................................................................................105

18.7 R

EGULATOR

PECIFICATIONS

.......................................................................................................................................105

19 DC S

PECIFICATIONS

..............................................................................................................................................................106

19.1 D

IGITAL

INS

...............................................................................................................................................................106

19.2 T

WISTED

AIR

NTERFACE

INS

...................................................................................................................................106

20 AC T

IMING

PECIFICATIONS

..................................................................................................................................................107

20.1 GMII M

ODE

RANSMIT

IMING

(1000BASE-T) ............................................................................................................107

20.2 GMII M

ODE

ECEIVE

IMING

(1000BASE-T) ..............................................................................................................108

20.3 MII T

RANSMIT

IMING

(100M

).................................................................................................................................109

Rev. 1.2.2 - 12 Sep 2003

- Page 5 of 136 -

型号	CIS8201-128LQA-C	CIS8201-128LQA-C-R	CIS8201-BKCR	CIS8201-BKC
描述	Interface Circuit, CMOS, PQFP128, 14 X 20 MM, 0.50 MM PITCH, LQFP-128	Interface Circuit, CMOS, PQFP128, 14 X 20 MM, 0.50 MM PITCH, LQFP-128	Interface Circuit, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, LBGA-100	Interface Circuit, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, LBGA-100
零件包装代码	QFP	QFP	BGA	BGA
包装说明	LFQFP,	LFQFP,	LBGA,	LBGA,
针数	128	128	100	100
Reach Compliance Code	compliant	compliant	compliant	compliant
JESD-30 代码	R-PQFP-G128	R-PQFP-G128	S-PBGA-B100	S-PBGA-B100
长度	20 mm	20 mm	11 mm	11 mm
功能数量	1	1	1	1
端子数量	128	128	100	100
最高工作温度	70 °C	70 °C	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFQFP	LFQFP	LBGA	LBGA
封装形状	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm	1.7 mm	1.7 mm
标称供电电压	1.5 V	1.5 V	1.5 V	1.5 V
表面贴装	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS
电信集成电路类型	INTERFACE CIRCUIT	INTERFACE CIRCUIT	INTERFACE CIRCUIT	INTERFACE CIRCUIT
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING	BALL	BALL
端子节距	0.5 mm	0.5 mm	1 mm	1 mm
端子位置	QUAD	QUAD	BOTTOM	BOTTOM
宽度	14 mm	14 mm	11 mm	11 mm
Base Number Matches	1	1	1	1

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