CLC425
Ultra Low Noise Wideband Op Amp
June 1999
N
CLC425
Ultra Low Noise Wideband Op Amp
General Description
The CLC425 combines a wide bandwidth (1.9GHz
GBW)
with very
low input noise (1.05nV/√
Hz, 1.6pA/√Hz)
and low dc errors (100µ
V
√
√
µ
V
OS
, 2µV/°C drift)
to provide a very precise, wide dynamic-range
µ
op amp offering closed-loop gains of
≥10.
Singularly suited for very wideband high-gain operation, the CLC425
employs a traditional voltage-feedback topology providing all the
benefits of balanced inputs, such as low offsets and drifts, as well
as a 96dB open-loop gain, a 100dB CMRR and a 95dB PSRR.
The CLC425 also offers great flexibility with its externally adjustable
supply current, allowing designers to easily choose the optimum
set of power, bandwidth, noise and distortion performance.
Operating from ±5V power supplies, the CLC425 defaults to a
15mA quiescent current, or by adding one external resistor, the
supply current can be adjusted to less than 5mA.
The CLC425's combination of ultra-low noise, wide gain-band-
width, high slew rate and low dc errors will enable applications in
areas such as medical diagnostic ultrasound, magnetic tape & disk
storage, communications and opto-electronics to achieve maximum
high-frequency signal-to-noise ratios.
The CLC425 is available in the following versions:
CLC425AJP
CLC425AJE
CLC425A8B
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
8-pin PDIP
8-pin SOIC
8-pin CERDIP,
MIL-STD-883, Level B
dice
dice, MIL-STD-883, Level B
5-pin SOT
Voltage Noise (nV/√Hz)
Features
s
s
s
s
s
s
s
s
s
1.9GHz gain-bandwidth product
1.05nV/√Hz input voltage noise
0.8pA/√Hz @ Icc < 5mA
100µV input offset voltage, 2µV/°C drift
350V/µs slew rate
15mA to 5mA adjustable supply current
Gain range ±10 to ±1,000V/V
Evaluation boards & simulation
macromodel
0.9dB NF @ R
s
= 700Ω
Instrumentation sense amplifiers
Ultrasound pre-amps
Magnetic tape & disk pre-amps
Photo-diode transimpedance amplifiers
Wide band active filters
Low noise figure RF amplifiers
Professional audio systems
Low-noise loop filters for PLLs
Equivalent Input Voltage Noise
10
Applications
s
s
s
s
s
s
s
s
CLC425ALC
-40°C to +85°C
CLC425AMC
-55°C to +125°C
CLC425AJM5
-40°C to +85°C
DESC SMD number : 5962-93259.
1.05nV/√Hz
1
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
Pinout
SOT23-5
V
o
V
EE
V
non-inv
V
inv
V
CC
Pinout
DIP & SOIC
NC
V
inv
V
non-inv
-V
cc
1
2
3
4
-
+
8 R
p
(optional)
7 +V
cc
6 V
out
5 NC
©
1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
CLC425 Electrical Characteristics
(V
PARAMETERS
Ambient Temperature
CONDITIONS
CLC425 AJ
CC
= ±5V; A
V
= +20; R
f
=499Ω; R
g
= 26.1Ω; R
L
= 100Ω;
unless noted
)
Ω
Ω
Ω
MIN/MAX RATINGS
-40 C
+25
°
C
+85
°
C
°
TYP
+25
°
C
UNITS
SYMBOL
FREQUENCY DOMAIN RESPONSE
gain bandwidth product
V
out
< 0.4V
pp
-3dB bandwidth
V
out
< 0.4V
pp
V
out
< 5.0V
pp
gain flatness
V
out
< 0.4V
pp
peaking
DC to 30MHz
rolloff
DC to 30MHz
linear phase deviation
DC to 30MHz
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.2%
overshoot
slew rate
0.4V step
2V step
0.4V step
2V step
1.9
95
40
0.3
0.1
0.7
3.7
22
5
350
- 53
- 75
35
1.05
1.6
0.9
96
± 100
±2
12
- 100
± 0.2
±3
95
100
15
2
6
1.5
1.9
5
± 3.8
± 3.4
± 3.8
80
80
1.5
75
30
0.7
0.7
1.5
4.7
30
12
250
48
65
1.25
4.0
1.5
75
30
0.5
0.5
1.5
4.7
30
10
250
48
65
1.25
2.5
1.0
50
20
0.7
0.7
2.5
7.0
40
12
200
46
60
1.8
2.5
GHz
MHz
MHz
dB
dB
°
ns
ns
%
V/µs
dBc
dBc
dBm
nV/√Hz
pA/√Hz
dB
dB
µV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
MΩ
kΩ
pF
pF
mΩ
V
V
V
mA
mA
GBW
SSBW
LSBW
GFP
GFR
LPD
TRS
TSS
OS
SR
HD2
HD3
IMD
VN
ICN
NF
AOL
VIO
DVIO
IB
DIB
IIO
DIIO
PSRR
CMRR
ICC
RINC
RIND
CINC
CIND
ROUT
VO
VOL
CMIR
IOP
ION
DISTORTION AND NOISE RESPONSE
1V
pp
, 10MHz
2
nd
harmonic distortion
3
rd
harmonic distortion
1V
pp
, 10MHz
10MHz
3
rd
order intermodulation intercept
equivalent noise input
voltage
1MHz to 100MHz
current
1MHz to 100MHz
noise figure
R
S
= 700Ω
STATIC DC PERFORMANCE
open-loop gain
*input offset voltage
average drift
*input bias current
average drift
input offset current
average drift
power supply rejection ratio
common mode rejection ratio
*supply current
DC
DC
DC
R
L
=
∞
77
± 1000
8
40
- 250
3.4
± 50
82
88
18
0.6
1
2
3
50
± 3.5
± 2.8
± 3.4
70
45
86
± 800
____
20
____
2.0
____
88
92
16
1.6
3
2
3
10
± 3.7
± 3.2
± 3.5
70
55
86
± 1000
4
20
- 120
2.0
± 25
86
90
16
1.6
3
2
3
10
± 3.7
± 3.2
± 3.5
70
55
MISCELLANEOUS PERFORMANCE
input resistance
common-mode
differential-mode
input capacitance
common-mode
differential-mode
output resistance
closed loop
output voltage range
R
L
=
∞
R
L
=100Ω
input voltage range
common mode
output current
source
sink
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
V
cc
I
out
short circuit protected to ground, however maximum reliabiliy
is obtained if I
out
does not exceed...
Miscellaneous Ratings
±7V
125mA
±V
cc
+150
°
C
Recommended gain range
Notes:
* AJ : 100% tested at +25°C.
±10 to ±1,000V/V
common-mode input voltage
maximum junction temperature
operating temperature range:
AJ
storage temperature range
lead temperature (soldering 10 sec)
ESD (human body model)
Package Thermal Resistance
Package
AJP
AJE
A8B
AJM5
θ
JC
70°C/W
65°C/W
45°C/W
115°C/W
θ
JA
125°C/W
145°C/W
135°C/W
185°C/W
-40°C to +85°C
-65°C to +150°C
+300°C
1000V
Reliability Information
Transistor count
31
http://www.national.com
2
3
http://www.national.com
(µA)
http://www.national.com
4
+V
cc
V
in
R
s
V
s
R
T
6.8µF
3
7
0.1µF
CLC425
2
6.8µF
6
V
out
Total Input Noise vs. Source Resistance
In order to determine maximum signal-to-noise ratios
from the CLC425, an understanding of the interaction
between the amplifier's intrinsic noise sources and the
noise arising from its external resistors is necessary.
Figure 3 describes the noise model for the non-inverting
amplifier configuration showing all noise sources. In
addition to the intrinsic input voltage noise (e
n
) and
current noise (i
n
=i
n+
=i
n-
) sources, there also exists ther-
mal voltage noise (
e
t
=
4
k
TR
) associated with each of
the external resistors. Equation 1 provides the general
form for total equivalent input voltage noise density (e
ni
).
Equation 2 is a simplification of Equation 1 that assumes
4
-V
cc
R
s
eq
= R
s
|| R
T
R
g
A
v
= 1 +
0.1µF
R
f
R
f
R
g
Figure 1: Non-inverting Amplifier Configuration
Introduction
The CLC425 is a very wide gain-bandwidth, ultra-low
noise voltage feedback operational amplifier which en-
ables application areas such as medical diagnostic ultra-
sound, magnetic tape & disk storage and fiber-optics to
achieve maximum high-frequency signal-to-noise ratios.
The set of characteristic plots located in the "Typical
Performance" section illustrates many of the perfor-
mance trade-offs. The following discussion will enable
the proper selection of external components in order to
achieve optimum device performance.
Bias Current Cancellation
In order to cancel the bias current errors of the non-
inverting configuration, the parallel combination of the
gain-setting (R
g
) and feedback (R
f
) resistors should equal
the equivalent source resistance (R
seq
) as defined in
Figure 1. Combining this constraint with the non-invert-
ing gain equation also seen in Figure 1, allows both R
f
and R
g
to be determined explicitly from the following
equations: R
f
=A
v
R
seq
and R
g
=R
f
/(A
v
-1). When driven from
a 0Ω source, such as that from the output of an op amp,
the non-inverting input of the CLC425 should be isolated
with at least a 25Ω series resistor.
As seen in Figure 2, bias current cancellation is accom-
plished for the inverting configuration by placing a resis-
tor (R
b
) on the non-inverting input equal in value to the
resistance seen by the inverting input (R
f
||(R
g
+R
s
)). R
b
is
recommended to be no less than 25Ω for best CLC425
performance. The additional noise contribution of R
b
can
be minimized through the use of a shunt capacitor.
+V
cc
7
0.1µF
6.8µF
e
n
R
s
eq
√4kTR
s
eq
i
n
+
CLC425
i
n
-
R
g
R
f
√4kTR
f
√4kTR
g
4
kT
=
16.4
e
−
21
Joules
@
25
°
C
Figure 3: Non-inverting Amplifer Noise Model
e
ni
=
2
e
n
+
i
n
+
R
s
(
eq
)
2
+
4
kTR
s
eq
+
i
n
−
R
f
||
R
g
(
(
)
)
2
+
4
kT R
f
||
R
g
(
)
Equation 1: General Noise Equation
R
f
||R
g
= R
seq
for bias current cancellation. Figure 4
illustrates the equivalent noise model using this as-
sumption. Figure 5 is a plot of e
ni
against equivalent
source resistance (R
seq
) with all of the contributing volt-
age noise sources of Equation 2 shown. This plot gives
the expected e
ni
for a given R
seq
which assumes R
f
||R
g
=
R
seq
for bias current cancellation. The total equivalent
output voltage noise (e
no
) is e
ni
∗A
v
.
√4kT2R
s
eq
2R
s
eq
e
n
A
v
3
R
b
V
out
6
i
n
√2
CLC425
2
6.8µF
4
Figure 4: Noise Model with R
f
||R
g
= R
seq
V
in
R
s
V
s
A
v
= - R
f
R
g
R
g
-V
cc
0.1µF
R
f
e
ni
=
2
e
n
+
2
i
n
R
s
eq
(
)
2
+
4
kT
2
R
s
eq
(
)
Figure 2: Inverting Amplifier Configuration
Equation 2: Noise Equation with R
f
||R
g
= R
seq
5
http://www.national.com
