Comlinear CLC431/432
Dual Wideband Monolithic Op Amp with Disable
August 1996
N
Comlinear CLC431/432
Dual Wideband Monolithic Op Amp with Disable
General Description
The CLC431 and CLC432 current-feedback amplifiers provide wide
bandwidths and high slew rates for applications where board density
and power are key considerations. These amplifiers provide dc-
coupled small signal bandwidths exceeding 92MHz while consum-
ing only 7mA per channel. Operating from ±15V supplies, the
CLC431/432’s enhanced slew rate circuitry delivers large-signal
bandwidths with output voltage swings up to 28V
pp
. A wide range of
bandwidth-insensitive gains are made possible by virtue of the
CLC431 and CLC432’s current-feedback topology.
The large common-mode input range and fast settling time (70ns to
0.05%) make these amplifiers well suited for CCD & data telecom-
munication applications. The disable of the CLC431 can accommo-
date ECL or TTL logic levels or a wide range of user definable inputs.
With its fast enable/disable time (0.2µs/1µs) and high channel
isolation of 70dB at 10MHz, the CLC431 can easily be configured as
a 2:1 MUX. Many high performance video applications requiring
signal gain and/or switching will be satisfied with the CLC431/432
due to their very low differential gain and phase errors (less than
0.1% and 0.1°; A
V
=+2V/V at 4.43MHz into 150Ω load).
Quick 8ns rise and fall times on 10V pulses allow the CLC431/432
to drive either twisted pair or coaxial transmission lines over long
distances.
The CLC431/432's combination of low input voltage noise, wide
common-mode input voltage range and large output voltage swings
make them especially well suited for wide dynamic range signal
processing applications.
Features
s
s
s
s
s
Wide bandwidth: 92MHz (A
V
=+1)
62MHz (A
V
=+2)
Fast slew rate: 2000V/µs
Fast disable: 1µs to high-Z output
High channel isolation: 70dB at 10MHz
Single or dual supplies:
±5V
to ±16.5V
Video signal multiplexing
Twisted-pair differential driver
CCD buffer & level shifting
Discrete gain-select amplifier
Transimpedance amplifier
Applications
s
s
s
s
s
Typical Application
Discrete Gain Select Amplifier
Pinout
PDIP & SOIC
R
g
500Ω
R
f
500Ω
50Ω
R
i
½CLC431
50Ω
R
s
SELECT
R
i
1V
pp
@ 5MHz
50Ω
½CLC431
500Ω
R
f
R
g
125Ω
Channel 2 (Gain = 5)
50Ω
50Ω
50Ω
R
L
V
out
Channel 1 (Gain = 2)
CLC431
V
inv
1
1
V
non-inv
1
2
DIS1
3
-V
cc
4
DIS2
5
V
non-inv
2
6
V
inv
2
7
14
V
out
1
13
V
R
TTL
1
12
DIS1
11
+V
cc
10
DIS2
9
V
R
TTL
2
8
V
out
2
V
out
1
V
inv
1
V
non-inv
1
-Vcc
1
2
3
4
-
+
-
+
CLC432
8
7
6
5
+V
cc
V
out
2
V
inv
2
V
non-inv
2
©
1996 National Semiconductor Corporation
Printed in the U.S.A.
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CLC431/432 Electrical Characteristics
(V
PARAMETERS
Ambient Temperature
CONDITIONS
CLC431 & CLC432
TYP
+25
CC
=
±
15V; A
V
= +2; R
f
= R
g
=750Ω; R
L
= 100Ω;
unless noted
)
Ω
Ω
MIN/MAX RATINGS
+25
0 to +70
-40 to +85
UNITS
°C
NOTES
1
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
V
out
< 4.0V
pp
V
CC
=±5V
V
out
< 4.0V
pp
V
out
< 10V
pp
gain flatness
V
out
< 4.0V
pp
peaking
DC to 100MHz
rolloff
DC to 20MHz
linear phase deviation
DC to 30MHz
differential gain
4.43MHz, R
L
=150Ω
differential phase
4.43MHz, R
L
=150Ω
TIME DOMAIN RESPONSE
rise and fall time
10V step
overshoot
2V step
settling time
2V step to 0.05%
slew rate
V
out
= ±10V
DISTORTION AND NOISE RESPONSE
2
nd
harmonic distortion
2V
pp
, 1MHz
2V
pp
, 1MHz
3
rd
harmonic distortion
equivalent input noise
voltage
>1MHz
current, inverting
>1MHz
current, non-inverting
>1MHz
STATIC DC PERFORMANCE
input
offset voltage
average drift
bias current, non-inverting
average drift
bias current, inverting
average drift
power supply rejection ratio
DC
common-mode rejection ratio
DC
supply current
R
L
=
∞
, per channel
CLC431 disabled
R
L
=
∞
, per channel
MISCELLANEOUS PERFORMANCE
input
voltage range
common mode
resistance
non-inverting
capacitance
non-inverting
output
current
voltage range
R
L
≥
5kΩ
R
L
=100Ω
SWITCHING PERFORMANCE (CLC431)
switching time
turn on
turn off
DIS logic levels
single-ended mode
high input voltage (V
IH
)
low input voltage (V
IL
)
maximum current input
V
IH
> DIS > V
IL
|DIS-
DIS
|
differential mode
minimum differential voltage
ISOLATION
crosstalk, input referred
off isolation
10MHz
10MHz
62
62
28
0.05
0.0
0.3
0.12
0.12
8
5
70
2000
- 65
- 75
3.3
13
2.0
3
20
2
25
2
8
64
63
7.1
0.8
± 12.2
24
0.5
± 60
± 14.0
± 6.0
0.1
0.7
> 2.0
< 0.8
150
0.3
70
64
42
21
0.5
0.8
1.8
0.18
0.18
12
10
100
1500
37
20
0.7
0.8
2.0
0.2
0.23
13
12
110
1450
36
20
0.7
0.8
2.1
0.2
0.25
13
12
110
1400
MHz
MHz
MHz
dB
dB
°
%
°
ns
%
ns
V/µs
dBc
dBc
B
2
B
B
2
2
6
6
4.2
16
2.5
6
---
8
---
6
---
59
58
7.9
1.2
± 12.0
16
1
± 38
± 13.6
± 3.7
0.15
1.0
> 2.0
< 0.8
180
0.4
64
60
4.4
17
2.6
7
50
10
100
6
25
59
57
8.5
1.3
± 11.8
10
1
± 35
± 13.4
± 3.7
0.155
1.2
> 2.0
< 0.8
190
0.4
64
60
4.5
18
2.8
7
50
16
150
8
40
59
56
9.6
1.45
± 11.6
6
1
± 30
± 13.2
± 2.9
0.165
1.2
> 2.0
< 0.8
205
0.4
64
60
nV/√Hz
pA/√Hz
pA/√Hz
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
mA
V
MΩ
pF
mA
V
V
µs
µs
3
V
V
µA
4
V
dB
dB
A
A
A
B
A
A
5
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
supply voltage
short circuit current
common-mode input voltage
differential input voltage
maximum junction temperature
storage temperature
lead temperature (soldering 10 sec)
±16.5V
100mA
±V
cc
±10V
+200
°
C
-65°C to+150°C
+300°C
Notes
1) Tested and guaranteed with R
f
= 866Ω.CLC432 tested and guaranteed
with R
f
= 750Ω.
2) Spec is guaranteed for R
L
≥
500Ω.
3) V
RTTL
= 0, See text for single-ended mode of operation.
4) V
RTTL
= NC, See text for differential mode of operation
5) Spec is guaranteed for AJE; AJP & AIB yield 7dB lower.
6) Spec is tested with 2V
pp
, 10MHz and R
L
= 100Ω.
A) J-level: spec is 100% tested at +25°C, sample tested at +85°C.
L-level: spec is 100% wafer probed at 25°C.
B) J-level: spec is sample tested at 25°C.
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2
3
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Application Discussion
Introduction
The CLC431 and the CLC432 are dual wideband current-
feedback op amps that operate from single (+10V to
+33V) or dual (±5V to ±16.5) power supplies. The
CLC431 is equipped with a disable feature and is offered
in 14-pin DIP and SOIC packages. The CLC432 is
packaged in a standard 8-pin dual pinout and is offered
in an 8-pin DIP and SOIC. Evaluation boards are available
for each version of both devices. The evaluation boards
can assist in the device and/or application evaluation and
were used to generate the typical device performance
plots on the preceding pages.
Each of the CLC431/CLC432's dual channels provide
closely matched DC & AC electrical performance
characteristics making them ideal choices for wideband
signal processing. The CLC431, with its disable feature,
can easily be configured as a 2:1 mux or several can be
used to form a 10:1 mux without performance degradation.
The two closely-matched channels of the CLC432 can be
combined to form composite circuits for such applications
as filter blocks, integrators, transimpedance amplifiers
and differential line drivers and receivers.
Feedback Resistor Selection
The loop gain and frequency response for a current-
feedback operational amplifier is determined largely by
the feedback resistor (R
f
). Package parasitics also
influence ac response. Since the package parasitics of
the CLC431 and the CLC432 are different, the optimum
frequency and phase responses are obtained with different
values of feedback resistor (for A
V
=+2; CLC431: R
f
=866Ω,
CLC432: R
f
=750Ω). The Electrical Characteristics and
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Typical Performance plots are valid for both devices
under the specified conditions. Generally, lowering R
f
from its recommended value will peak the frequency
response and extend the bandwidth while increasing its
value will roll off the response. Reducing the value of R
f
too far below its recommended value will cause overshoot,
ringing and eventually oscillation. For more information
see Application Note OA-20 and OA-13.
In order to optimize the devices' frequency and phase
response for gains other than +2V/V it is recommended
to adjust the value of the feedback resistor. The two plots
found in the Typical Performance section entitled
"Recommended R
f
vs. Gain" provide the means of
selecting the feedback-resistor value that optimizes
frequency and phase response over the CLC431/
CLC432's gain range. Both plots show the value of R
f
approaching a nonzero minimum at high non-inverting
gains, which is characteristic of current-feedback op
amps and yields best results. The linear portion of the
two R
f
vs. Inverting-gain curves results from the limitation
placed on R
g
(i.e. R
g
≥
50Ω) in order to maintain an
adequate input impedance for the inverting configuration.
It should be noted that for stable operation a non-
inverting gain of +1 requires an R
f
equal to 1kΩ for both
the CLC431 and the CLC432.
CLC431 Disable Feature
The CLC431 disable feature can be operated either
single-endedly or differentially thereby accommodating a
wide range of logic families. There are three pins asso-
ciated with the disable feature of each of the CLC431's
two amplifiers:
DIS, DIS and V
RTTL
(please see pinout on
4
front page). Also note that both amplifiers are guaranteed
to be enabled if all three of these pins are unconnected.
Fig. 1 illustrates the single-ended mode of the CLC431's
disable feature for logic families such as TTL and CMOS.
In order to operate properly,
V
RTTL
must be grounded,
thereby biasing
DIS
to approximately +1.4V through the
two internal series diodes. For single-ended operation,
DIS
should be left floating. Applying a TTL or CMOS logic
"high" (i.e. >2.0Volts) to
DIS
will switch the tail current of
the differential pair to Q1 and "shut down" Q2 which
results in the
disabling
of that channel of the CLC431.
Alternatively, applying a logic "low" (i.e. <0.8Volts) toDIS
will switch the tail current from Q1 to Q2 effectively
enabling
that channel. If
DIS
is left floating under single-
ended operation, then the associated amplifier is guaran-
teed to be
disabled.
V
non-inv
V
inv
+V
CC
+V
CC
+
-
+V
CC
Fig. 2 illustrates the differential mode of the CLC431's
disable feature for ECL-type logic. In order for this mode
to operate properly,
V
RTTL
must be left floating while
DIS
and
DIS
are to be connected directly to the ECL gate as
illustrated. Applying a differential logic "high" (DIS -
DIS
≥
0.4Volts) switches the tail current of the differential pair
from Q2 to Q1 and results in the
disabling
of that CLC431
channel. Alternatively, applying a differential logic "low"
(DIS -
DIS
≤
-0.4Volts) switches the tail current of the
differential pair from Q1 to Q2 and results in the
enabling
of that same channel. The internal clamp, mentioned
above, also protects against excessive differential volt-
ages up to 30Volts while limiting input currents to <3mA.
DC Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot
be cancelled and each contributes to the total DC offset
voltage at the output by the following equation:
V
offset
= ±
I
bn
∗
R
s
R
f
1
+
+
V
io
R
g
R
f
1
+
+
I
∗
R
R
bi f
g
V
out
100kΩ
TTL
CMOS
DIS
Q
1
Q
2
100kΩ
DIS
V
RTTL
The input resistor R
s
is that resistance seen when looking
from the non-inverting input back towards the source. For
inverting DC-offset calculations, the source resistance
seen by the input resistor R
g
must be included in the
output offset calculation as a part of the non-inverting
gain equation. Application note OA-7 gives several circuits
for DC offset correction.
Layout Considerations
It is recommended that the decoupling capacitors (0.1µF
ceramic and 6.8µF electrolytic) should be placed as close
as possible to the power supply pins to insure a proper
high-frequency low impedance bypass. Careful attention
to circuit board layout is also necessary for best
performance. Of particular importance is the control of
parasitic capacitances (to ground) at the output and
invering input pins. See CLC431/432 Evaluation Board
literature for more information.
Applications Circuits
2:1 Video Mux (CLC431)
Fig. 3 illustrates the connections necessary to configure
the CLC431 as a 2:1 multiplexer in a 75Ω system. Each
of the two CLC431's amplifiers is configured with a non-
inverting gain of +2V/V using 634Ω feedback (R
f
) and
gain-setting (R
g
) resistors. The feedback resistor value is
lower than that recommended in order to compensate for
the reduction of loop-gain that results from the inclusion
of the 50Ω resistor (R
i
) in the feedback loop. This 50Ω
resistor serves to isolate the output of the active channel
from the impedance of the inactive channel yet does not
affect the low output impedance of the active channel.
Notice that for proper operationV
RTTL
1
(pin 13) is grounded
and
V
RTTL
2
(pin 9) is unconnected. The pins associated
with the disable feature are to be connected as follows:
DIS1
and
DIS2
(pins 3 & 10) are connected together as
well as
DIS2
and
DIS1
(pins 5 & 12). Channel 1 is
selected with the application of a logic "low" to SELECT
while a logic "high" selects Channel 2.
5
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½CLC431
Fig. 1
The disable feature of the CLC431 is such that
DIS
and
DIS
have common-mode input voltage ranges of (+V
CC
)
to (-V
CC
+3V) and are so guaranteed over the commercial
temperature range. Internal clamps (not shown) protect
the
DIS
input from excessive input voltages that could
otherwise cause damage to the device. This condition
occurs when enough source current flows into the node
so as to allow
DIS
to rise to V
CC
. This clamp is activated
once
DIS
exceeds
DIS
by 1.5Volts and guarantees that
V
DIS
(ground referenced) does not exceed 4.7Volts.
V
non-inv
V
inv
+V
CC
+V
CC
+
-
+V
CC
V
out
100kΩ
DIS
Q
1
ECL
510Ω
-5V
Q
2
100kΩ
DIS
½CLC431
V
RTTL
510Ω
-5V
Fig. 2
