Small Signal Transistor
PROCESS
CP555
PNP - Saturated Switch Transistor Chip
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
GROSS DIE PER 4 INCH WAFER
75,330
PRINCIPAL DEVICE TYPES
CMPT3640
CMPT4209
2N4209
BACKSIDE COLLECTOR
EPITAXIAL PLANAR
15 X 10 MILS
8 MILS
3.6 X 2.4 MILS
3.6 X 2.4 MILS
Al - 20,000Å
Au - 15,000Å
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R3 (21-August 2006)
PROCESS
CP555
Typical Electrical Characteristics
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R3 (21-August 2006)