High Speed Super Low Power SRAM
256k Word x 16 Bit
CS16LV40973
Revision History
Rev. No.
1.0
1.1
1.2
1.3
1.4
History
Initial issue
Add in 48 mini_BGA - 6x7mm
Revise 48 mini_BGA 6x7mm to 6x8mm
Revise AC/DC Char.
Add in 48 mini_BGA - 6x7mm
Issue Date
Jan.18, 2005
Apr. 08, 2005
Oct. 25, 2005
Mar. 11, 2008
Jun. 25, 2008
Remark
1
Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256k Word x 16 Bit
CS16LV40973
n
GENERAL DESCRIPTION
The CS16LV40973 is a high performance; high speed and super low power CMOS Static
Random Access Memory organized as 262,144 words by 16bits and operates from a wide range of
2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 3.0V operation. Easy
memory expansion is provided by an active LOW chip enable inputs (/CE1, CE2) and active LOW
output enable (/OE).
The CS16LV40973 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS16LV40973 is available in JEDEC standard 44-pin
TSOP 2 package and 48 ball Mini_BGA
–
6x7mm.
n
FEATURES
Ø
Ø
Ø
Ø
Ø
Ø
Wide operation voltage : 2.7 ~ 3.6V
Ultra low power consumption : 3mA＠1MHz (Typ.) , Vcc=3.0V.
0.5 uA (Typ.) CMOS standby current
High speed access time : 55/70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 1.5V.
Easy expansion with (/CE1, CE2) and /OE options.
Ø
n
Product Family
Part No.
Operating Temp Vcc. Range Speed (ns)
Standby (Typ.)
0.5uA
(Vcc = 3.0V)
44 TSOP 2
48 BGA_6x7mm
55/ 70
1.0uA
(Vcc= 3.0V)
Dice
Package Type
0~70
o
C
CS16LV40973
-40~85 C
o
55/ 70
2.7~3.6
2
Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256k Word x 16 Bit
CS16LV40973
n
PIN CONFIGURATION
n
FUNCTIONAL BLOCK DIAGRAM
3
Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256k Word x 16 Bit
CS16LV40973
Function
n
PIN DESCRIPTIONS
Name
A0
–
A17
Type
Input
Address inputs for selecting one of the 262,144 x 16 bit words in the RAM
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active
/CE1, CE2
Input
when data read from or write to the device. If either chip enable is not active, the
device is deselected and in a standby power down mode. The DQ pins will be in
high impedance state when the device is deselected.
The Write enable input is active LOW. It controls read and write operations. With
/WE
Input
the chip selected, when /WE is HIGH and /OE is LOW, output data will be present
on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written
into the selected memory location.
The output enable input is active LOW. If the output enable is active while the chip
/OE
Input
is selected and the write enable is inactive, data will be present on the DQ pins and
they will be enabled. The DQ pins will be in the high impedance state when /OE is
inactive.
/LB, /UB
DQ0~DQ15
Vcc
Gnd
Input
I/O
Power
Power
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n
TRUTH TABLE
MODE
Standby
/CE1
X
H
Output Disabled
L
CE2
L
X
H
/WE
X
X
H
X
/OE
X
X
H
X
/LB
X
X
X
H
L
Read
L
H
H
L
H
L
L
Write
L
H
L
X
H
L
/UB
X
X
X
H
L
L
H
L
L
H
D
OUT
High Z
D
OUT
D
IN
X
D
IN
D
OUT
D
OUT
High Z
D
IN
D
IN
X
High Z
High Z
DQ0~7
High Z
DQ8~15
High Z
Vcc Current
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
4
Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256k Word x 16 Bit
CS16LV40973
(1)
n
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Rating
-0.5 to Vcc+0.5
-40 to +125
-60 to +150
1.0
30
Unit
V
O
O
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
W
mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
n
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0~70 C
-40~85 C
o
o
Vcc
2.7V ~3.6V
2.7V ~ 3.6V
1. Overshoot : Vcc +2.0V in case of pulse width
≦20ns.
2. Undershoot : - 2.0V in case of pulse width
≦20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
n
CAPACITANCE
(1)
(TA = 25
o
C, f =1.0 MHz)
Symbol
C
IN
C
DQ
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
=0V
V
I/O
=0V
MAX.
6
8
Unit
pF
pF
1. This parameter is guaranteed, and not 100% tested.
5
Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
汽车电子
