Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
5 differential 2.5V/3.3V LVPECL outputs
•
Selectable differential CLKx, nCLKx inputs
•
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following differential input levels: LVPECL, LVDS, LVHSTL,
HCSL, SSTL
•
Maximum output frequency: 700MHz
•
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 1.8ns (maximum)
•
RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS85314I-11 is a low skew, high perfor-
mance 1-to-5 Differential-to-2.5V/3.3V LVPECL
HiPerClockS™
fanout buffer and a member of the HiPerClock ™
S
family of High Performance Clock Solutions from
ICS. The ICS85314I-11 has two selectable dif-
ferential clock inputs. The CLK0, nCLK0 and CLK1, nCLK1
pairs can accept most standard differential input levels. The
clock enable is internally synchronized to eliminate runt clock
pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics make
the ICS85314I-11 ideal for those applications demanding well
defined performance and repeatability.
B
LOCK
D
IAGRAM
nCLK_EN
D
Q
CK
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Q2
nQ2
Q3
nQ3
Q4
nQ4
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nCLK_EN
V
CC
nCLK1
CLK1
RESERVED
nCLK0
CLK0
CLK_SEL
V
EE
0
0
1
1
Q0
nQ0
Q1
nQ1
ICS85314I-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
ICS85314I-11
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
85314AGI-11
www.icst.com/products/hiperclocks.html
1
REV. B MARCH 22, 2005
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
Type
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Do not connect.
Input
Input
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 8
9, 10
11
12
13
14
15
16
17
18, 20
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
EE
CLK_SEL
CLK0
nCLK0
RESERVED
CLK1
nCLK1
V
CC
Output
Output
Output
Output
Output
Power
Input
Input
Input
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock
19
nCLK_EN
Input
Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced
high. LVTTL / LVCMOS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Power
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
85314AGI-11
www.icst.com/products/hiperclocks.html
2
REV. B MARCH 22, 2005
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
Inputs
Outputs
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
Q0:Q4
Enabled
Enabled
Disabled; LOW
nQ0:nQ4
Enabled
Enabled
Disabled; HIGH
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
nCLK_EN
0
0
1
CLK_SEL
0
1
0
1
1
CLK1, nCLK1
Disabled; LOW
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs
as described in Table 3B.
Disabled
Enabled
nCLK0, nCLK1
CLK0, CLK1
nCLK_EN
nQ0:nQ4
Q0:Q4
F
IGURE
1. nCLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK0 or CLK1
0
1
nCLK0 or nCLK1
1
0
Q0:Q4
LOW
HIGH
Outputs
nQ0:nQ4
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Polarity
Non Inver ting
Non Inver ting
85314AGI-11
www.icst.com/products/hiperclocks.html
3
REV. B MARCH 22, 2005
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
80
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
nCLK_EN, CLK_SEL
nCLK_EN, CLK_SEL
CLK_SEL, nCLK_EN
CLK_SEL, nCLK_EN
V
IN
= V
CC
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-150
-5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLKx, nCLKx is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
85314AGI-11
www.icst.com/products/hiperclocks.html
4
REV. B MARCH 22, 2005
Integrated
Circuit
Systems, Inc.
ICS85314I-11
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 1.0
V
CC
- 1.7
1.0
Units
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Output Skew; NOTE 2, 5
RMS Phase Jitter (Random);
NOTE 4
Par t-to-Par t Skew; NOTE 3, 5
Setup Time
Hold Time
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
700
IJ 700MHz
1.0
1.4
1.8
30
Integration Range:
(12kHz - 20MHz)
nCLK_EN to CLK
nCLK_EN to CLK
20% to 80%
50
50
200
700
55
0.05
250
Units
MHz
ns
ps
ps
ps
ps
ps
ps
ps
t
sk(o)
tjit (Ø)
t
sk(pp)
t
S
t
H
t
R
/ t
F
odc
Output Duty Cycle
IJ 700MHz
45
All parameters measured at f
MAX
unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Please refer to Phase Noise Plot.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
85314AGI-11
www.icst.com/products/hiperclocks.html
5
REV. B MARCH 22, 2005
嵌入式系统
