CXD3412GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description
The CXD3412GA is a timing generator and CCD
signal processor IC for the ICX412 CCD image sensor.
Features
•
Timing generator functions
•
Horizontal drive frequency 22.5MHz
(base oscillation frequency 45MHz)
•
Supports frame readout/draft (sextuple speed)/
AF (auto focus)
•
High-speed/low-speed shutter function
•
Horizontal and vertical drivers for CCD image
sensor
•
CCD signal processor functions
•
Correlated double sampling
•
Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (–6 to +42dB)
•
10-bit A/D converter
•
Chip Scale Package (CSP):
CSP allows vast reduction in the CCD camera
block footprint
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX412 (Type 1/1.8, 3240K pixels)
96 pin LFLGA (Plastic)
Absolute Maximum Ratings
•
Supply voltage
V
DD
a, V
DD
b, V
DD
c, V
DD
d V
SS
– 0.3 to +7.0
V
DD
e, V
DD
f, V
DD
g
VL
VH
•
Input voltage (analog)
V
IN
•
Input voltage (digital)
V
I
•
Output voltage
V
O1
V
O2
V
O3
•
Operating temperature
Topr
•
Storage temperature
Tstg
V
SS
– 0.3 to +4.0
–10.0 to V
SS
VL – 0.3 to +26.0
V
SS
– 0.3 to V
DD
+ 0.3
V
SS
– 0.3 to V
DD
+ 0.3
V
SS
– 0.3 to V
DD
+ 0.3
VL – 0.3 to V
SS
+ 0.3
VL – 0.3 to VH + 0.3
–20 to +75
–55 to +125
V
V
V
V
V
V
V
V
V
°C
°C
Recommended Operating Conditions
•
Supply voltage
V
DD
d
3.0 to 5.5
V
DD
a, V
DD
b, V
DD
c, V
DD
d,
V
DD
e, V
DD
f, V
DD
g
3.0 to 3.6
VM
0.0
VH
14.5 to 15.5
VL
–7.0 to –8.0
•
Operating temperature
Topr
–20 to +75
V
V
V
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02217-PS
CXD3412GA
Block Diagram
TEST3
TEST4
TEST5
DV
DD1
DV
DD2
AV
DD3
AV
DD4
DV
SS3
DV
SS1
DV
SS2
AV
SS3
AV
SS4
AV
SS5
SCK2
A1 A2 C7 D8 D7
B8 B6 B9 A6 C5
A3 A4 B4
SEN2
SSI2
NC
NC
C3
C2
C1
A5 C4
B5
E2 F2 F3
E3 F1
C4 C8
AV
DD5
A9
AV
SS6
A8
C7 B7
C8 A7
C9 C6
CCDIN C9
AV
DD1
E9
AV
DD2
E8
AV
SS1
D9
AV
SS2
E7
XSHPI
F9
XSHDI
F8
PBLKI
F7
XSHP
G9
XSHD
G8
PBLK
G7
XRS H7
V
DD4
H8
V
DD2
K7
RG K8
V
SS2
K9
V
DD3
H9
H1 J8
H2 J9
V
SS3
J7
ID/EXP N9
WEN M9
L2
VH M5
VM L4
VL M6
Serial Port
Register
V Driver
SSI1
M1 SCK1
N1 SEN1
SSG
L8
SSGSL
Latch
1/2
Selector
Pulse Generator
CDS
PGA
ADC
Latch
DAC
Serial Port
Register
B3
B2
B1
D0 (LSB)
D1
D2
C3 D3
C2 D4
C1 D5
D3 D6
D2 D7
D1 D8
E1
Preblanking
Dummy Pixel
Auto Zero
Black Level
Auto Zero
D9 (MSB)
ADCLKI
CLPOBI
CLPDMI
V
SS4
ADCLK
CLPOB
CLPDM
V
SS5
OSCI
OSCO
CKI
CKO
MCKO
G1
G2
G3
L3
H1
H2
H3
J3
L1
K1
J1
J2
K2
N8 SNCSL
M8 M3 M7
L5 N5 M4 L6
N6 N4 N7
N2 M2
Selector
L9
K3 L7
N3
V
SS1
V
DD1
TEST1
TEST2
–2–
V
DD5
V
SS6
RST
V1A
V1B
V3A
V3B
SUB
HD
VD
V2
V4
CXD3412GA
Pin Configuration
(Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
NC
D2
D5
D8
D9
DV
SS2
ADCLKI
ADCLK
CKI
OSCO
OSCI
SCK1
SEN1
1
NC
D1
D4
D7
DV
DD1
DV
SS3
CLPOBI
CLPOB
CKO
MCKO
SSI1
VD
HD
2
SCK2
D0
D3
D6
DV
SS1
DV
DD2
CLPDMI
CLPDM
V
SS5
V
DD5
V
SS4
TEST1
V
SS6
3
SSI2
SEN2
TEST4
TEST3
TEST5
AV
SS5
AV
SS4
AV
DD4
C9
C8
C7
C3
C1
AV
SS2
PBLKI
PBLK
XRS
V
SS3
V
DD2
AV
SS6
AV
DD3
C4
C2
AV
DD2
XSHDI
XSHD
V
DD4
H1
RG
SSGSL
RST
SNCSL
8
AV
DD5
AV
SS3
CCDIN
AV
SS
1
AV
DD1
XSHPI
XSHP
V
DD3
H2
V
SS2
V
DD1
WEN
ID/EXP
9
VM
V2
V4
4
V1A
VH
V1B
5
V3A
VL
V3B
6
V
SS1
TEST2
SUB
7
–3–
CXD3412GA
Pin Description
Pin
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D7
D8
D9
E1
E2
E3
E7
Symbol
NC
NC
SCK2
SSI2
TEST3
AV
SS4
C8
AV
SS6
AV
DD5
D2
D1
D0
SEN2
TEST5
AV
DD4
C7
AV
DD3
AV
SS3
D5
D4
D3
TEST4
AV
SS5
C9
C3
C4
CCDIN
D8
D7
D6
C1
C2
AV
SS1
D9
DV
DD1
DV
SS1
AV
SS2
I/O
—
—
I
I
I
—
—
—
—
O
O
O
I
I
—
—
—
—
O
O
O
I
—
—
—
—
I
O
O
O
—
—
—
O
—
—
—
No connected. (Open)
No connected. (Open)
CCD signal processor block serial interface clock input. (Schmitt trigger)
CCD signal processor block serial interface data input. (Schmitt trigger)
CCD signal processor block test input 3. Connect to DV
SS
.
CCD signal processor block analog GND.
Capacitor connection.
CCD signal processor block analog GND.
CCD signal processor block analog power supply.
ADC output.
ADC output.
ADC output (LSB).
CCD signal processor block serial interface enable input. (Schmitt trigger)
CCD signal processor block test input 5. Connect to DV
DD
.
CCD signal processor block analog power supply.
Capacitor connection.
CCD signal processor block analog power supply.
CCD signal processor block analog GND.
ADC output.
ADC output.
ADC output.
CCD signal processor block test input 4. Connect to DV
SS
.
CCD signal processor block analog GND.
Capacitor connection.
Capacitor connection.
Capacitor connection.
CCD output signal input.
ADC output.
ADC output.
ADC output.
Capacitor connection.
Capacitor connection.
CCD signal processor block analog GND.
ADC output (MSB).
CCD signal processor block digital power supply. (Power supply for ADC)
CCD signal processor block digital GND. (GND for ADC)
CCD signal processor block analog GND.
–4–
Description
CXD3412GA
Pin
No.
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
H1
H2
H3
H7
H8
H9
J1
J2
J3
J7
J8
J9
K1
K2
K3
K7
K8
K9
L1
L2
Symbol
AV
DD2
AV
DD1
DV
SS2
DV
SS3
DV
DD2
PBLKI
XSHDI
XSHPI
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
ADCLK
CLPOB
CLPDM
XRS
V
DD4
V
DD3
CKI
CKO
V
SS5
V
SS3
H1
H2
OSCO
MCKO
V
DD5
V
DD2
RG
V
SS2
OSCI
SSI1
I/O
—
—
—
—
—
I
I
I
I
I
I
O
O
O
O
O
O
O
—
—
I
O
—
—
O
O
O
O
—
—
O
—
I
I
Description
CCD signal processor block analog power supply.
CCD signal processor block analog power supply.
CCD signal processor block digital GND.
CCD signal processor block digital GND.
CCD signal processor block digital power supply.
Pulse input for horizontal and vertical blanking period pulse cleaning.
(Schmitt trigger)
CCD data level sample-and-hold pulse input. (Schmitt trigger)
CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
Clock input for analog/digital conversion. (Schmitt trigger)
CCD optical black signal clamp pulse input. (Schmitt trigger)
CCD dummy signal clamp pulse input. (Schmitt trigger)
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD data level sample-and-hold pulse output.
CCD precharge level sample-and-hold pulse output.
Clock output for analog/digital conversion.
Logical phase can be adjusted by serial interface data.
CCD optical black signal clamp pulse output.
Horizontal/vertical OB pattern can be changed by serial interface data.
CCD dummy signal clamp pulse output.
Sample-and-hold pulse output for analog/digital conversion phase alignment.
Timing generator block digital power supply. (Power supply for CDS block)
Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2)
Inverter input.
Inverter output.
Timing generator block digital GND.
Timing generator block digital GND.
CCD horizontal register clock output.
CCD horizontal register clock output.
Inverter output for oscillation. When not used, leave open or connect a capacitor.
System clock output for signal processor IC.
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block digital power supply. (Power supply for RG)
CCD reset gate pulse output.
Timing generator block digital GND.
Inverter input for oscillation. When not used, fix to low.
Timing generator block serial interface data input. Schmitt trigger input.
–5–
