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CY2CP1504ZXC

Low Skew Clock Driver, 2DL Series, 4 True Output(s), 4 Inverted Output(s), PDSO20, 4.40 MM, LEAD FREE, MO-153, TSSOP-20

器件类别:逻辑    逻辑   

厂商名称:Cypress(赛普拉斯)

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Cypress(赛普拉斯)
零件包装代码
TSSOP
包装说明
TSSOP, SSOP20,.25
针数
20
Reach Compliance Code
compliant
ECCN代码
EAR99
Factory Lead Time
1 week
其他特性
ALSO OPERATES WITH 3.135V TO 3.465V SUPPLY
系列
2DL
输入调节
MUX
JESD-30 代码
R-PDSO-G20
JESD-609代码
e3
长度
6.5 mm
逻辑集成电路类型
LOW SKEW CLOCK DRIVER
湿度敏感等级
3
功能数量
1
反相输出次数
4
端子数量
20
实输出次数
4
最高工作温度
70 °C
最低工作温度
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
SSOP20,.25
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度(摄氏度)
260
电源
2.5/3.3 V
Prop。Delay @ Nom-Sup
0.48 ns
传播延迟(tpd)
0.48 ns
认证状态
Not Qualified
Same Edge Skew-Max(tskwd)
0.03 ns
座面最大高度
1.1 mm
最大供电电压 (Vsup)
2.625 V
最小供电电压 (Vsup)
2.375 V
标称供电电压 (Vsup)
2.5 V
表面贴装
YES
温度等级
COMMERCIAL
端子面层
Matte Tin (Sn)
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
宽度
4.4 mm
最小 fmax
250 MHz
文档预览
CY2CP1504
1:4 LVCMOS to LVPECL Fanout Buffer
with Selectable Clock Input
1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Features
Functional Description
The CY2CP1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The CY2CP1504 can select between
two separate LVCMOS input clocks using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The device has a
fully differential internal architecture that is optimized to achieve
low additive jitter and low skew at operating frequencies of up to
250 MHz.
For a complete list of related documentation,
click here.
Select one of two low-voltage complementary metal oxide
semiconductor (LVCMOS) inputs to distribute to four
low-voltage positive emitter-coupled logic (LVPECL) output
pairs
30-ps maximum output-to-output skew
480-ps maximum propagation delay
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 250 MHz operation
Synchronous clock enable function
20-Pin thin shrunk small outline package (TSSOP) package
2.5-V or 3.3-V operating voltage
[1]
Commercial and industrial operating temperature range
Logic Block Diagram
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56313 Rev. *J
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 13, 2016
CY2CP1504
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................3
Absolute Maximum Ratings ............................................4
Operating Conditions .......................................................4
DC Electrical Specifications ............................................5
Thermal Resistance ..........................................................5
AC Electrical Specifications ............................................6
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Diagram ............................................................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC®Solutions ........................................................14
Cypress Developer Community .................................14
Technical Support ......................................................14
Document Number: 001-56313 Rev. *J
Page 2 of 14
CY2CP1504
Pin Configurations
Figure 1. 20-pin TSSOP Package pinout
Pin Definitions
Pin No.
1
2
3
Pin Name
V
SS
CLK_EN
IN_SEL
Pin Type
Power
Input
Input
Ground
Synchronous clock enable. LVCMOS/low-voltage transistor-transistor logic (LVTTL).
When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are held high
Input clock select pin. LVCMOS/LVTTL;
When IN_SEL = Low, input IN0 is active
When IN_SEL = High, input IN1 is active
LVCMOS input clock. Active when IN_SEL = Low
No connection
Input
Power
Output
Output
LVCMOS input clock. Active when IN_SEL = High
Power supply
LVPECL complementary output clocks
LVPECL output clocks
Description
4
5, 7, 8, 9
6
10, 13, 18
11, 14, 16, 19
12, 15, 17, 20
IN0
NC
IN1
V
DD
Q(0:3)#
Q(0:3)
Input
Document Number: 001-56313 Rev. *J
Page 3 of 14
CY2CP1504
Absolute Maximum Ratings
Parameter
V
DD
V
IN[2]
V
OUT[2]
T
S
ESD
HBM
L
U
UL–94
MSL
Description
Supply voltage
Input voltage, relative to V
SS
Nonfunctional
Nonfunctional
Condition
Min
–0.5
–0.5
Max
4.6
lesser of
4.0 or
V
DD
+ 0.4
lesser of
4.0 or
V
DD
+ 0.4
150
Unit
V
V
DC output or I/O voltage, relative Nonfunctional
to V
SS
Storage temperature
Nonfunctional
–0.5
V
–55
2000
°C
V
Electrostatic discharge (ESD)
JEDEC STD 22-A114-B
protection (Human body model)
Latch up
Flammability rating
Moisture sensitivity level
At 1/8 in
Meets or exceeds JEDEC
Spec JESD78B IC latch up test
V-0
3
Operating Conditions
Parameter
V
DD
T
A
t
PU
Description
Supply voltage
Ambient operating temperature
Power ramp time
2.5 V supply
3.3 V supply
Commercial
Industrial
Power-up time for V
DD
to reach minimum
specified voltage (power ramp must be
monotonic)
Condition
Min
2.375
3.135
0
–40
0.05
Max
2.625
3.465
70
85
500
Unit
V
V
°C
°C
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required.
Document Number: 001-56313 Rev. *J
Page 4 of 14
CY2CP1504
DC Electrical Specifications
(V
DD
= 3.3 V ± 5% or 2.5 V ± 5%; T
A
= 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
I
DD
V
IH1
V
IL1
V
IH2
V
IL2
I
IH
I
IL
V
OH
V
OL
R
P
C
IN
Description
Operating supply current
Input high voltage, All inputs
Input low voltage, All inputs
Input high voltage, All inputs
Input low voltage, All inputs
Input high current, All inputs
Input low current, All inputs
LVPECL output high voltage
LVPECL output low voltage
Internal pull-up/pull-down
resistance
Input capacitance
V
DD
= 3.3 V
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 2.5 V
Input = V
DD[3]
Input = V
SS[3]
Terminated with 50
to V
DD
– 2.0
[4]
Terminated with 50
to V
DD
– 2.0
[4]
CLK_EN has pull-up only
IN_SEL has pull-down only
Measured at 10 MHz; per pin
Condition
All LVPECL outputs floating (internal I
DD
)
Min
2.0
–0.3
1.7
–0.3
–150
Max
61
V
DD
+ 0.3
0.8
V
DD
+ 0.3
0.7
150
Unit
mA
V
V
V
V
A
A
V
V
k
pF
V
DD
– 1.20 V
DD
– 0.70
V
DD
– 2.0 V
DD
– 1.63
60
165
3
Thermal Resistance
Parameter
[5]
θ
JA
θ
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
20-pin TSSOP Unit
80
16
°C/W
°C/W
Notes
3. Positive current flows into the input pin, negative current flows out of the input pin.
4. Refer to
Figure 2 on page 7.
5. These parameters are guaranteed by design and are not tested.
Document Number: 001-56313 Rev. *J
Page 5 of 14
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参数对比
与CY2CP1504ZXC相近的元器件有:CY2CP1504ZXCT、CY2CP1504ZXIT。描述及对比如下:
型号 CY2CP1504ZXC CY2CP1504ZXCT CY2CP1504ZXIT
描述 Low Skew Clock Driver, 2DL Series, 4 True Output(s), 4 Inverted Output(s), PDSO20, 4.40 MM, LEAD FREE, MO-153, TSSOP-20 Low Skew Clock Driver, 2DL Series, 4 True Output(s), 4 Inverted Output(s), PDSO20, 4.40 MM, LEAD FREE, MO-153, TSSOP-20 Low Skew Clock Driver, 2DL Series, 4 True Output(s), 4 Inverted Output(s), PDSO20, 4.40 MM, LEAD FREE, MO-153, TSSOP-20
是否Rohs认证 符合 符合 符合
厂商名称 Cypress(赛普拉斯) Cypress(赛普拉斯) Cypress(赛普拉斯)
零件包装代码 TSSOP TSSOP TSSOP
包装说明 TSSOP, SSOP20,.25 TSSOP, SSOP20,.25 TSSOP, SSOP20,.25
针数 20 20 20
Reach Compliance Code compliant compliant compliant
ECCN代码 EAR99 EAR99 EAR99
其他特性 ALSO OPERATES WITH 3.135V TO 3.465V SUPPLY ALSO OPERATES WITH 3.135V TO 3.465V SUPPLY ALSO OPERATES WITH 3.135V TO 3.465V SUPPLY
系列 2DL 2DL 2DL
输入调节 MUX MUX MUX
JESD-30 代码 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20
JESD-609代码 e3 e3 e3
长度 6.5 mm 6.5 mm 6.5 mm
逻辑集成电路类型 LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
湿度敏感等级 3 3 3
功能数量 1 1 1
反相输出次数 4 4 4
端子数量 20 20 20
实输出次数 4 4 4
最高工作温度 70 °C 70 °C 85 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP TSSOP TSSOP
封装等效代码 SSOP20,.25 SSOP20,.25 SSOP20,.25
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
峰值回流温度(摄氏度) 260 260 260
电源 2.5/3.3 V 2.5/3.3 V 2.5/3.3 V
Prop。Delay @ Nom-Sup 0.48 ns 0.48 ns 0.48 ns
传播延迟(tpd) 0.48 ns 0.48 ns 0.48 ns
认证状态 Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.03 ns 0.03 ns 0.03 ns
座面最大高度 1.1 mm 1.1 mm 1.1 mm
最大供电电压 (Vsup) 2.625 V 2.625 V 2.625 V
最小供电电压 (Vsup) 2.375 V 2.375 V 2.375 V
标称供电电压 (Vsup) 2.5 V 2.5 V 2.5 V
表面贴装 YES YES YES
温度等级 COMMERCIAL COMMERCIAL INDUSTRIAL
端子面层 Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
端子形式 GULL WING GULL WING GULL WING
端子节距 0.65 mm 0.65 mm 0.65 mm
端子位置 DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 30 30
宽度 4.4 mm 4.4 mm 4.4 mm
最小 fmax 250 MHz 250 MHz 250 MHz
Factory Lead Time 1 week 1 week -
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