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CY62147G18-55BVXIT

SRAM MICROPOWER SRAMS

器件类别：存储   

厂商名称：Cypress(赛普拉斯)

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器件参数
参数名称
属性值
Product Attribute
Attribute Value
制造商
Manufacturer
Cypress(赛普拉斯)
产品种类
Product Category
SRAM
RoHS
Details
系列
Packaging
Reel
Moisture Sensitive
Yes
NumOfPackaging
1
工厂包装数量
Factory Pack Quantity
2000
文档预览
CY62147G/CY621472G
CY62147GE MoBL
®
4-Mbit (256K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
■
■
High speed: 45 ns/55 ns
Ultra-low standby power
❐
Typical standby current: 3.5
A
❐
Maximum standby current: 8.7
A
Embedded ECC for single-bit error correction
[1, 2]
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V
to 5.5 V
1.0-V data retention
TTL-compatible inputs and outputs
Error indication (ERR) pin to indicate 1-bit error detection and
correction
Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O
0
through I/O
15
and
address on A
0
through A
17
pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O
8
through I/O
15
and BLE controls I/O
0
through I/O
7
.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O
0
through I/O
15
).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O
0
through I/O
15
) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE
1
HIGH/CE
2
LOW for a dual chip enable device), or
control signals are de-asserted (OE, BLE, BHE).
The device also has a unique Byte Power down feature, where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enables, thereby saving power.
On the CY62147GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)
[1]
. See the
Truth
Table – CY62147G/CY62147GE on page 16
for a complete
description of read and write modes.
The logic block diagrams are on page 2.
■
■
■
■
■
■
Functional Description
CY62147G and CY62147GE are high-performance CMOS
low-power (MoBL) SRAM devices with embedded ECC. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62147GE device includes an
ERR pin that signals an error-detection and correction event
during a read cycle.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE
1
as low and CE
2
as HIGH.
Product Portfolio
Product
[3]
Features and
Options
(see the Pin
Configurations
section)
Power Dissipation
Range
V
CC
Range (V)
Speed (ns)
Operating I
CC
, (mA)
f = f
max
Typ
[4]
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
55
45
15
15
Max
20
20
Standby, I
SB2
(µA)
Typ
[4]
3.5
3.5
Max
10
8.7
CY62147G(E)18 Single or dual
CY62147G(E)30 Chip Enables
CY621472G30
Optional ERR
CY62147G(E)
pin
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer
AN88889
for details.
3.
The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer
Ordering Information on page 17.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for a V
CC
range of 1.65 V–2.2 V),
V
CC
= 3 V (for V
CC
range of 2.2 V–3.6 V), and V
CC
= 5 V (for V
CC
range of 4.5 V–5.5 V), T
A
= 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-92847 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 13, 2018
CY62147G/CY621472G
CY62147GE MoBL
®
Logic Block Diagram – CY62147G
ECC ENCODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFER
ROW  DECODER
ECC DECODER
SENSE 
AMPLIFIERS
MEMORY
ARRAY
I/O
0
‐I/O
7
I/O
8
‐I/O
15
COLUMN DECODER
A10
A11
A12
A13
A14
A15
A16
A17
BHE
WE
OE
BLE
CE
2
CE
1
Logic Block Diagram – CY62147GE
ECC ENCODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFER
ROW  DECODER
ECC DECODER
SENSE 
AMPLIFIERS
ERR
I/O
0
‐I/O
7
I/O
8
‐I/O
15
MEMORY
ARRAY
COLUMN DECODER
A10
A11
A12
A13
A14
A15
A16
A17
BHE
WE
OE
BLE
CE
2
CE
1
Document Number: 001-92847 Rev. *K
Page 2 of 22
CY62147G/CY621472G
CY62147GE MoBL
®
Contents
Pin Configuration – CY62147G ........................................ 4
Pin Configuration – CY62147GE ..................................... 5
Pin Configuration – CY621472G ...................................... 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads and Waveforms ....................................... 9
Data Retention Characteristics ..................................... 10
Data Retention Waveform .............................................. 10
AC Switching Characteristics ....................................... 11
Switching Waveforms .................................................... 12
Truth Table – CY62147G/CY62147GE ........................... 16
ERR Output – CY62147GE ............................................. 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-92847 Rev. *K
Page 3 of 22
CY62147G/CY621472G
CY62147GE MoBL
®
Pin Configuration – CY62147G
Figure 1. 48-ball VFBGA pinout (Dual Chip Enable without Figure 2. 48-ball VFBGA pinout (Single Chip Enable without
ERR), CY62147G
[5]
ERR), CY62147G
[5]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
V
CC
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Figure 3. 44-pin TSOP II pinout (Single Chip Enable without ERR), CY62147G
[5]
A4
A3
A2
A1
A0
/ CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
44- TSOP-II
Notes
5. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 001-92847 Rev. *K
Page 4 of 22
CY62147G/CY621472G
CY62147GE MoBL
®
Pin Configuration – CY62147GE
Figure 4. 48-ball VFBGA pinout
(Dual Chip Enable with ERR), CY62147GE
[6, 7]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
3
A
0
A
3
A
5
A
17
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
V
CC
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Figure 5. 48-ball VFBGA pinout
(Single Chip Enable with ERR), CY62147GE
[6, 7]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
ERR
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
I/O
12
ERR
I/O
13
NC
A
8
A
14
A
12
A
9
Figure 6. 44-pin TSOP II pinout (Single Chip Enable with ERR), CY62147GE
[6, 7]
A4
A3
A2
A1
A0
/CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
ERR
A8
A9
A10
A11
A12
44- TSOP-II
Notes
6. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
7. ERR is an output pin.
Document Number: 001-92847 Rev. *K
Page 5 of 22
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参数对比
与CY62147G18-55BVXIT相近的元器件有：CY62147G30-55BVXET、CY62147G30-45B2XIT、CY621472G30-45ZSXA、CY62147G30-55BVXE、CY62147G30-45ZSXA、CY62147GE30-45BVXIT、CY62147GE18-55BVXIT、CY62147G18-55ZSXT。描述及对比如下：
型号 CY62147G18-55BVXIT CY62147G30-55BVXET CY62147G30-45B2XIT CY621472G30-45ZSXA CY62147G30-55BVXE CY62147G30-45ZSXA CY62147GE30-45BVXIT CY62147GE18-55BVXIT CY62147G18-55ZSXT
描述 SRAM MICROPOWER SRAMS SRAM MICROPOWER SRAMS SRAM MICROPOWER SRAMS SRAM Micropower SRAMs SRAM MICROPOWER SRAMS SRAM Micropower SRAMs IC SRAM 4M PARALLEL IC SRAM 4M PARALLEL Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, TSOP2-44
技术 - - - CMOS CMOS CMOS SRAM - 异步 SRAM - 异步 CMOS
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器件捷径:
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ
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