Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
V
CC
3.3V
±
10%
3.3V
±
10%
3.3V
±
10%
Electrical Characteristics
Over the Operating Range
1020CV33-10 1020CV33-12 1020CV33-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS[2]
I
CC
Description
Test Conditions
Min.
2.4
0.4
2.0
−0.3
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
Com’l / Ind’l
Automotive
Output Leakage
Current
Output Short
Circuit Current
V
CC
Operating
Supply Current
Com’l / Ind’l
Automotive
−1
-
−1
-
V
CC
+
0.3
0.8
+1
-
+1
-
−300
90
-
15
-
5
-
2.0
–0.3
–1
-
–1
-
Max.
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
-
+1
-
–300
85
-
15
-
5
-
2.0
–0.3
–1
–20
–1
–20
Max.
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
+20
+1
+20
–300
80
85
15
20
5
10
Max.
Unit
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l / Ind’l
Automotive
Com’l / Ind’l
Automotive
Com’l / Ind’l
Automotive
I
SB1
Automatic CE
Max. V
CC
, CE > V
IH
Power-down Current V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
—TTL Inputs
Max. V
CC
,
Automatic CE
Power-down Current CE > V
CC
– 0.3V,
—CMOS Inputs
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
I
SB2
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
Thermal Resistance
[3]
Parameter
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
44-pin TSOP-II
76.92
15.86
Unit
°C/W
°C/W
Θ
JA
Θ
JC
Notes:
1. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 0.5V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05133 Rev. *D
Page 3 of 9
CY7C1020CV33
AC Test Loads and Waveforms
[4]
R 317Ω
3.3V
OUTPUT
30 pF
R2
351Ω
High-Z characteristics:
3.3V
OUTPUT
5 pF
ALL INPUT PULSES
90%
GND
10%
90%
10%
R2
351Ω
R 317Ω
(a)
3.0V
(c)
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
Switching Characteristics
Over the Operating Range
[4]
1020CV33-10
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU[7]
t
PD[7]
t
DBE
t
LZBE
t
HZBE
Write Cycle
[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[5]
WE LOW to High-Z
[5, 6]
Byte Enable to End of Write
7
10
8
7
0
0
7
5
0
3
5
8
12
9
8
0
0
8
6
0
3
6
9
15
10
10
0
0
10
8
0
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to
OE HIGH to
CE LOW to
CE HIGH to
Low-Z
[5]
High-Z
[5, 6]
Low-Z
[5]
High-Z
[5, 6]
0
10
5
0
5
0
6
3
5
0
12
6
0
7
0
5
3
6
0
15
7
3
10
5
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
1020CV33-12
Min.
Max.
1020CV33-15
Min.
Max.
Unit
CE LOW to Power-up
CE HIGH to Power-down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
6. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7. This parameter is guaranteed by design and is not tested.
8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05133 Rev. *D
Page 4 of 9
CY7C1020CV33
Switching Waveforms
Read Cycle No. 1
[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[10, 11]
ADDRESS
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
IISB
SB
IICC
CC
t
HZOE
HIGH
IMPEDANCE
DATA OUT
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
10. WE is HIGH for Read cycle.
11. Address valid prior to or coincident with CE transition LOW.
