E
n
n
n
n
n
n
Two 32-Byte Write Buffers
2
µs
per Byte Effective
Programming Time
Operating Voltage
5 V V
CC
5 V V
PP
70 ns Read Access Time (16 Mbit)
90 ns Read Access Time (32 Mbit)
High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
System Performance Enhancements
STS Status Output
Industry-Standard Packaging
SSOP and TSOP (16 Mbit)
SSOP (32 Mbit)
ADVANCED INFORMATION
WORD-WIDE
FlashFile™ MEMORY FAMILY
28F160S5, 28F320S5
Includes Extended Temperature Specifications
n
n
Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
Block Erase Cycles
100,000 at 0 °C to +70 °C
(Commercial)
10,000 at –40 °C to +85 °C
(Extended)
Enhanced Data Protection Features
Absolute Protection with V
PP
= GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
Configurable x8 or x16 I/O
Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
ETOX™ V Nonvolatile Flash
Technology
n
n
n
n
Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, nonvolatile, read/write storage
solutions for a wide range of applications. The word-wide memories are available at various densities in the
same package type. Their symmetrically-blocked architecture, voltage, and extended cycling provide highly
flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend
capabilities provide an ideal solution for code or data storage applications. For secure code storage
applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM,
the word-wide memories offer three levels of protection: absolute protection with V
PP
at GND, selective block
locking, and program/erase lockout during power transitions. These alternatives give designers ultimate
control of their code security needs.
This family of products is manufactured on Intel’s 0.4
µm
ETOX™ V process technology. It comes in the
industry-standard 56-lead SSOP. In addition, the 16-Mb device is available in the industry-standard 56-lead
TSOP package.
January 1998
Order Number: 290609-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F160S3 and 28F320S3 may contain design defects or errors known as errata. Current characterized errata are available
on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-4725
or call 1-800-548-4725
or visit Intel’s website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION 1997, 1998
CG-041493
*Third-party brands and names are the property of their respective owners.
E
28F160S5, 28F320S5
CONTENTS
PAGE
PAGE
4.8 Write to Buffer Command ......................... 26
4.9 Byte/Word Program Command................. 26
4.10 STS Configuration Command................. 27
4.11 Block Erase Suspend Command ............ 27
4.12 Program Suspend Command ................. 27
4.13 Set Block Lock-Bit Command ................. 28
4.14 Clear Block Lock-Bits Command ............ 28
5.0 DESIGN CONSIDERATIONS ...................... 38
5.1 Three-Line Output Control........................ 38
5.2 STS and WSM Polling .............................. 38
5.3 Power Supply Decoupling ........................ 38
5.4 V
PP
Trace on Printed Circuit Boards........ 38
5.5 V
CC
, V
PP
, RP# Transitions........................ 38
5.6 Power-Up/Down Protection ...................... 38
6.0 ELECTRICAL SPECIFICATIONS................ 39
6.1 Absolute Maximum Ratings ...................... 39
6.2 Operating Conditions................................ 39
6.3 Capacitance ............................................. 40
6.4 DC Characteristics ................................... 40
6.5 AC Characteristics—Read-Only
Operations............................................... 44
6.6 AC Characteristics—Write Operations...... 46
6.7 Erase, Write, and Lock-Bit Configuration
Performance............................................ 49
7.0 ADDITIONAL INFORMATION ..................... 50
7.1 Device Nomenclature and Ordering
Information .............................................. 50
7.2 Intel Documentation ................................. 51
1.0 INTRODUCTION ........................................... 5
1.1 New Features............................................. 5
1.2 Product Overview....................................... 5
1.3 Pinout and Pin Description ......................... 6
2.0 PRINCIPLES OF OPERATION ..................... 9
2.1 Data Protection ........................................ 10
3.0 BUS OPERATION ....................................... 10
3.1 Read ........................................................ 10
3.2 Output Disable ......................................... 11
3.3 Standby.................................................... 11
3.4 Deep Power-Down ................................... 11
3.5 Read Query Operation ............................. 11
3.6 Read Identifier Codes Operation .............. 11
3.7 Write ........................................................ 12
4.0 COMMAND DEFINITIONS .......................... 12
4.1 Read Array Command.............................. 16
4.2 Read Query Mode Command................... 16
4.2.1 Query Structure Output ..................... 16
4.2.2 Query Structure Overview ................. 18
4.2.3 Block Status Register ........................ 19
4.2.4 CFI Query Identification String........... 20
4.2.5 System Interface Information............. 21
4.2.6 Device Geometry Definition ............... 22
4.2.7 Intel-Specific Extended Query Table . 23
4.3 Read Identifier Codes Command ............. 24
4.4 Read Status Register Command.............. 24
4.5 Clear Status Register Command.............. 25
4.6 Block Erase Command ............................ 25
4.7 Full Chip Erase Command ....................... 25
ADVANCED INFORMATION
3
28F160S5, 28F320S5
E
REVISION HISTORY
Description
Number
-001
-002
Original version
Added commercial temperature information throughout the document.
Updated address in Figure 5.
Added descriptive information for CFI query to Section 4.2.5,
System Interface Information
Updated addresses and added descriptive information in Table 9 and Table 10.
Corrected documentation errors in Table 15 and Table 16.
Updated Figure 6. Modified decision diamond for checking counter.
Corrected documentation errors in Figure 11 and Figure 12.
Updated Table 19 to include commercial and extended temperature range specifications.
Updated note 4 in Table 19 for clarification.
Updated Table 20 to show 16 Mb/32 Mb specifications more clear and corrected
documentation error.
Corrected documentation error in Figure 17 and Table 23.
Updated package designators and order codes in Appendix A.
Corrected error in datasheet designator
-003
4
ADVANCED INFORMATION
E
1.0
1.1
•
•
•
•
28F160S5, 28F320S5
Specifically designed for 5 V systems, the
28F160S5 and 28F320S5 support read and write
operation with V
CC
equal to V
PP
. Coupled with this
capability, high programming performance is
achieved through small, highly-optimized write
buffer operations. Additionally, the dedicated V
PP
pin gives complete data protection when V
PP
≤
V
PPLK
.
A Common Flash Interface (CFI) permits OEM-
specified software algorithms to be used for entire
families of devices. This allows device-
independent, JEDEC ID-independent, and forward-
and backward-compatible software support for the
specified flash device families. Flash vendors can
standardize their existing interfaces for long-term
compatibility.
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement).
Additionally,
SCS
provides
the
highest
system/device data transfer rates and minimizes
device and system-level implementation costs.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal device operation. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within t
WHQV2/EHQV2
independent of other blocks. Each block can be
independently erased 100,000 times in the
commercial temperature range (0 °C to +70 °C) and
10,000 times in the extended temperature range
(–40 °C to +85 °C). Block erase suspend allows
system software to suspend block erase to read or
write data from any other block.
Data is programmed in byte, word or page
increments. Program suspend mode enables the
system to read data or execute code from any other
flash memory array location.
The device incorporates two Write Buffers of 32
bytes (16 words) to allow optimum-performance
data programming. This feature can improve
system program performance by up to eight times
over non-buffer programming.
5
INTRODUCTION
This datasheet contains Word-Wide FlashFile™
memory (28F160S5, 28F320S5) specifications.
Section 1.0 provides a flash memory overview.
Sections 2.0 through 5.0 describe the memory
organization and functionality. Section 6.0 covers
electrical specifications for extended temperature
product offerings. Finally, Section 7.0 provides
ordering and reference information.
New Features
The Word-Wide FlashFile memory family maintains
basic compatibility with Intel’s 28F016SA and
28F016SV. Key enhancements include:
Common Flash Interface (CFI) Support
Scaleable Command Set (SCS) Support
S5 Technology
Enhanced Suspend Capabilities
They share a compatible status register, basic
software commands, and pinout. These similarities
enable a clean migration from the 28F016SA or
28F016SV. When upgrading, it is important to note
the following differences:
•
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
New software commands.
To take advantage of the 5 V technology on the
28F160S5
and
28F320S5,
allow
V
PP
connection to V
CC
. The 28F160S5 and
28F320S5 FlashFile memories do not support a
12 V V
PP
option.
•
•
1.2
Product Overview
The Word-Wide FlashFile memory family provides
density upgrades with pinout compatibility for the
16- and 32-Mbit densities. They are high-
performance memories arranged as 1 Mword and
2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of
8 bits. This data is grouped in thirty-two and sixty-
four 64-Kbyte blocks that can be erased, locked,
and unlocked in-system. Figure 1 shows the block
diagram, and Figure 4 illustrates the memory
organization.
ADVANCED INFORMATION
