3 * Half Bridge Controller for System Optimization
ADVANCE PRODUCT INFORMATION – Mar. 20, 2013
E523.01B, 02B, 11B, 12B
Features
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•
•
•
•
•
•
•
•
•
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Applications
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•
•
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Dead-time generation (dynamical change via SPI)
IC supply voltage range 7 to 28V (peak 42V)
STOP/START-systems: limited operation down to 5V
Sleep mode current 20µA (typ.)
µC power supply 3,3V or 5V, up to 70mA direct load,
for >70mA with external boost transistor
Adjustable window-watchdog and reset generation
LIN2.2A-transceiver, compatible down to LIN1.3 or
PWM interface, bidirectional with error-feedback
LIN high-speed “FLASH-Mode”
Motor current measurement amplifier output
Over-current switch-off (dynamical change via SPI)
FET short-circuit protections (dyn. change via SPI)
Smart wake-up via BUS interface or KL15 ( pin S )
Configurable over-/ under-voltage protections
QFN: Junction temp. -40°C..+150°C ( 170°C peak)
BLDC(EC) motor control , multiple DC motor control
Fuel, Hydraulic, Oil and Water pumps
Cooling fans, HVAC fans, positioning systems
Turbo charger adjustment
General Description
This IC controls up to 3 NMOS half bridges for driving
BLDC motors, DC motors, or other loads. It's also pos-
sible to drive small loads directly at battery supply.
The IC supports an external µC with a power supply
(3.3V or 5V), reset-generator and watchdog .
The supply output current can be "boosted" with an
external transistor. For controlling the motor a dynamic-
ally programmable, very precise dead time generation
and a current measurement amplifier are implemented,
as well as diagnostic functions like detection of over cur-
rent (programmable threshold), over-temperature,
over-/under-voltage and short-circuits (programmable
threshold) and VBAT and temperature measurement.
Two product versions with a “state of the art” LIN2.2A,
or bidirectional PWM-interface are available. The LIN
interface supports a “FLASH-Mode” to upload a new
firmware to an external µC. The LIN2.2A interface is
also compatible down to LIN1.3. High junction temperat-
ures up to 170°C are allowed. Versions driving 2 NMOS
half bridges are available with E523.02B and E523.12B.
Ordering information
Product
ID
Feature
Packages
QFN44L7, QSOP44,
QFN48L7
see above
see above
see above
E523.01B LIN 2.x or PWM
interface
E523.11B PWM interface only
E523.02B .01B for 2 half-bridges
E523.12B .11B for 2 half-bridges
Typical Application Circuit
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
Data Sheet QM-No.: 25DS0006E.02
3 * Half Bridge Controller for System Optimization
ADVANCE PRODUCT INFORMATION – Mar. 20, 2013
E523.01B, 02B, 11B, 12B
Functional Diagram
Pin Configuration
QFN44L7 Pin Configuration, transparent top view, not to scale
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
2 / 71
Data Sheet QM-No.: 25DS0006E.02
3 * Half Bridge Controller for System Optimization
ADVANCE PRODUCT INFORMATION – Mar. 20, 2013
E523.01B, 02B, 11B, 12B
Pin Configuration (continued )
QFN48L7 Pin Configuration, transparent top view, not to scale.
with >0,6mm distance between VBAT, VBATS, BUS to ground
.
QSOP44 Pin Configuration, transparent top view, not to scale
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
3 / 71
Data Sheet QM-No.: 25DS0006E.02
3 * Half Bridge Controller for System Optimization
ADVANCE PRODUCT INFORMATION – Mar. 20, 2013
E523.01B, 02B, 11B, 12B
Pin Description
pin number pin number pin number
QFN44L7 QFN48L7
QSOP44
1
2
3
4
5
6
1
2
3
4
5
6
6
7
8
9
10
11
Name
PWMH3
PWMH2
PWMH1
TXD
RXD
PWML3
(WDTrig)
Type
①
I
I
I
I
O
I
Description
high side control signal, half bridge 3
( in version E523.02B,12B this pin has to
be connected to GND )
high side control signal, half bridge 2
high side control signal, half bridge 1
Bus interface transmit signal
Bus interface receive signal
low side control signal, half bridge 3
( or watchdog trigger )
( in version E523.02B,12B this pin can be
used as watchdog trigger input or it has
to be connected to GND )
low side control signal, half bridge 2
low side control signal, half bridge 1
external clock
SPI select (low active)
SPI data input
SPI data output
SPI clock input
interrupt output
VCC output voltage selection 3.3V / 5V
reset for external controller, low active,
open drain
must not be connected externally
analogue input voltage
Bus interface terminal
must not be connected externally
Bus interface ground
must not be connected externally
power supply sense input
must not be connected externally
power ground
KL-15 wake up
high side supply, half bridge 3
( in version E523.02B,12B this pin has to
be connected to GND )
high side gate drive output, half bridge 3
( in version E523.02B,12B this pin has to
be connected to GND )
motor phase, half bridge 3
( in version E523.02B,12B this pin has to
be connected to GND )
7
8
9
10
11
12
13
14
15
-
16
17
-
18
-
19
-
20
21
22
23
7
8
9
10
11
12
13
14
15
16
-
17
18
19
20
21
22
23
24
25
26
12
13
14
15
16
17
18
19
20
-
21
22
-
23
-
24
-
25
26
27
28
PWML2
PWML1
CLK
CSB
SI
SO
SCLK
VSEL
NRES
nc
VIN
BUS
nc
BUSGND
nc
VBATS
nc
PGND2
S
D3
GH3
I
I
I
I
I
O
I
I
O
I
I/O
S
I
S
I
S
O
24
27
29
M3
I
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG
4 / 71
Data Sheet QM-No.: 25DS0006E.02
3 * Half Bridge Controller for System Optimization
ADVANCE PRODUCT INFORMATION – Mar. 20, 2013
E523.01B, 02B, 11B, 12B
Pin Description (continued)
pin number pin number pin number
QFN44L7 QFN48L7
QSOP44
25
28
30
Name
GL3
Type
①
O
Description
low side gate drive output, half bridge 3
( in version E523.02B,12B this pin has to
be left open, no connection to any poten-
tial or signal is allowed )
high side supply, half bridge 2
high side gate drive output, half bridge 2
motor phase, half bridge 2
low side gate drive output, half bridge 2
high side supply, half bridge 1
high side gate drive output, half bridge 1
motor phase, half bridge 1
low side gate drive output, half bridge 1
debug and test mode activation
to be welded to GND in application
power ground
gate voltage supply output
must not be connected externally
power supply input
must not be connected externally
internal supply voltage
supply output for external µC or external
boost transistor
- in QFN48L7 bonded together with
VCC, no boost transistor use is
possible due to this limitation
sense input of VCC voltage supply
positive terminal measurement amplifier
negative terminal measurement amplifier
measurement amplifier output
ground
to be connected to GND and with optimal
thermal coupling
26
27
28
29
30
31
32
33
34
35
36
-
37
-
38
39
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
31
32
33
34
35
36
37
38
39
40
41
-
42
-
43
44
D2
GH2
M2
GL2
D1
GH1
M1
GL1
T
PGND1
VG
nc
VBAT
nc
VDD
VCCP
S
O
I
O
S
O
I
O
I
S
S
S
I/O
O
40
41
42
43
44
die paddle
44
45
46
47
48
die paddle
1
2
3
4
5
-
VCC
IP
IM
IO
GND
GND
I
I
I
O
S
S
①
S = Supply, I/O = Input/Output
Note:
Pins with identical names have to be connected.
GND, BUSGND, PGND1, PGND2 have to be connected externally and with die paddle in shortest way.
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
