Section I. Cyclone FPGA
Family Data Sheet
This section provides designers with the data sheet specifications for
Cyclone devices. The chapters contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Cyclone devices.
This section contains the following chapters:
■
■
■
■
■
Chapter 1. Introduction
Chapter 2. Cyclone Architecture
Chapter 3. Configuration & Testing
Chapter 4. DC & Switching Characteristics
Chapter 5. Reference & Ordering Information
Revision History
The table below shows the revision history for
Chapters 1
through
5.
Chapter(s)
1
Date / Version
August 2005 v1.3
October 2003
v1.2
September 2003
v1.1
May 2003 v1.0
Minor updates.
Changes Made
Added 64-bit PCI support information.
Updated LVDS data rates to 640 Mbps from
311 Mbps.
Updated RSDS feature information.
Added document to Cyclone Device Handbook.
Altera Corporation
Section I–1
Preliminary
Cyclone FPGA Family Data Sheet
Cyclone Device Handbook, Volume 1
Chapter(s)
2
Date / Version
August 2005 v1.4
February 2005
v1.3
Minor updates.
Changes Made
Updated JTAG chain limits. Added test vector
information.
Corrected Figure 2-12.
Added a note to Tables 2-17 through 2-21
regarding violating the setup or hold time.
Updated phase shift information.
Added 64-bit PCI support information.
Updated LVDS data rates to 640 Mbps from
311 Mbps.
Added document to Cyclone Device Handbook.
October 2003
v1.2
September 2003
v1.1
May 2003 v1.0
3
August 2005 V1.2 Minor updates.
February 2005
V1.1
May 2003 v1.0
Updated JTAG chain limits. Added information
concerning test vectors.
Added document to Cyclone Device Handbook.
Minor updates.
Updated information on Undershoot voltage.
Updated Table 4-2.
Updated Table 4-3.
Updated the undershoot voltage from 0.5 V to
2.0 V in Note 3 of Table 4-16.
Updated Table 4-17.
Added extended-temperature grade device
information. Updated Table 4-2.
Updated I
C C 0
information in Table 4-3.
Added clock tree information in Tab;e 4-19.
Finalized timing information for EP1C3 and
EP1C12 devices. Updated timing information in
Tables 4-25 through 4-26 and Tables 4-30
through 4-51.
Updated PLL specifications in Table 4-52.
Updated timing information. Timing finalized for
EP1C6 and EP1C20 devices. Updated
performance information. Added PLL Timing
section.
Added document to Cyclone Device Handbook.
Minor updates.
Updated Figure 5-1.
Added document to Cyclone Device Handbook.
4
August 2005 v1.5
February 2005
v1.4
January 2004
v.1.3
October 2003
v.1.2
July 2003 v1.1
May 2003 v1.0
5
August 2005 v1.2
February 2005
v1.1
May 2003 v1.0
Section I–2
Preliminary
Altera Corporation
1. Introduction
C51001-1.3
Introduction
The Cyclone
TM
field programmable gate array family is based on a 1.5-V,
0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 640 megabits per second (Mbps), and 66- and
33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for
interfacing with and supporting ASSP and ASIC devices. Altera also
offers new low-cost serial configuration devices to configure Cyclone
devices.
The following shows the main sections in the Cyclone FPGA Family Data
Sheet:
Section
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Embedded Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Global Clock Network & Phase-Locked Loops. . . . . . . . . . . 2–29
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39
Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . . 2–55
IEEE Std. 1149.1 (JTAG) Boundary Scan Support . . . . . . . . . . 3–1
SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3–5
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Altera Corporation
August 2005
1–1
Preliminary
Cyclone Device Handbook, Volume 1
Features
The Cyclone device family offers the following features:
■
■
■
■
■
■
■
■
■
■
■
■
2,910 to 20,060 LEs, see
Table 1–1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66- and 33-MHz, 64- and 32-bit PCI standard
High-speed (640 Mbps) LVDS I/O support
Low-speed (311 Mbps) LVDS I/O support
311-Mbps RSDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
Altera
®
MegaCore
®
functions and Altera Megafunctions Partners
Program (AMPP
SM
) megafunctions.
Table 1–1. Cyclone Device Features
Feature
LEs
M4K RAM blocks (128
×
36 bits)
Total RAM bits
PLLs
Maximum user I/O pins
(1)
Note to
Table 1–1:
(1)
This parameter includes global clock pins.
EP1C3
2,910
13
59,904
1
104
EP1C4
4,000
17
78,336
2
301
EP1C6
5,980
20
92,160
2
185
EP1C12
12,060
52
239,616
2
249
EP1C20
20,060
64
294,912
2
301
1–2
Preliminary
Altera Corporation
August 2005
Features
Cyclone devices are available in quad flat pack (QFP) and space-saving
FineLine
®
BGA packages (see
Table 1–2
through
1–3).
Table 1–2. Cyclone Package Options & I/O Pin Counts
Device
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Notes to
Table 1–2:
(1)
(2)
TQFP: thin quad flat pack.
PQFP: plastic quad flat pack.
Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the
EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package)
100-Pin TQFP 144-Pin TQFP 240-Pin PQFP
256-Pin
324-Pin
400-Pin
(1)
(1), (2)
(1)
FineLine BGA FineLine BGA FineLine BGA
65
104
249
98
185
173
185
185
249
233
301
301
Vertical migration means you can migrate a design from one device to
another that has the same dedicated pins, JTAG pins, and power pins, and
are subsets or supersets for a given package across device densities. The
largest density in any package has the highest number of power pins; you
must use the layout for the largest planned density in a package to
provide the necessary power pins for migration.
For I/O pin migration across densities, cross-reference the available I/O
pins using the device pin-outs for all planned densities of a given package
type to identify which I/O pins can be migrated. The Quartus
®
II
software can automatically cross-reference and place all pins for you
when given a device migration list. If one device has power or ground
pins, but these same pins are user I/O on a different device that is in the
migration path,the Quartus II software ensures the pins are not used as
user I/O in the Quartus II software. Ensure that these pins are connected
to the appropriate plane on the board. The Quartus II software reserves
I/O pins as power pins as necessary for layout with the larger densities
in the same package having more power pins.
Altera Corporation
August 2005
1–3
Preliminary
