APEX 20K
®
Programmable Logic
Device Family
Data Sheet
August 1999, ver. 2.01
Features...
s
Preliminary
Information
s
Industry’s first programmable logic device (PLD) incorporating
System-on-a-Programmable-Chip
TM
integration
–
MultiCore
TM
architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
– Embedded system block (ESB) implementation of product-term
logic used for combinatorial-intensive functions
– LUT logic used for register-intensive functions
– ESB used to implement memory functions, including first-in
first-out (FIFO) buffers, dual-port RAM, and content-
addressable memory (CAM)
High density
– 100,000 to 1 million typical gates (see
Table 1)
–
Up to 38,400 logic elements (LEs)
–
Up to 327,680 RAM bits that can be used without reducing
available logic
–
Up to 2,560 product-term-based macrocells
Table 1. APEX 20K Device Features
Feature
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
Notes:
(1)
(2)
Notes (1), (2)
EP20K600E EP20K1000E EP20K1500E
EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E
EP20K100
EP20K200
EP20K400
162,000 263,000
404,000
526,000
728,000 1,052,000 1,537,000 1,771,520 2,524,416
60,000
2,560
16
32,768
256
204
100,000
4,160
26
53,248
416
252
160,000
6,400
40
81,920
640
316
200,000
8,320
52
106,496
832
382
300,000
11,520
72
147,456
1,152
408
400,000
16,640
104
212,992
1,664
502
600,000
24,320
152
311,296
2,432
624
1,000,000 1,500,000
38,400
160
327,680
2,560
716
54,720
228
466,944
3,648
858
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to 48,000
additional gates.
This information is preliminary.
Altera Corporation
A-DS-APEX20K-02.01
1
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
...and More
Features
s
s
s
Designed for low-power operation
–
1.8-V and 2.5-V supply voltage (see
Table 2)
–
MultiVolt
TM
I/O interface support to interface with 1.8-V, 2.5-V,
and 3.3-V devices (see
Table 2)
–
ESB offering programmable power-saving mode
Flexible clock management circuitry with phase-locked loop (PLL)
– Built-in low-skew clock tree
– Up to eight global clock signals
– ClockLock
TM
feature reducing clock delay and skew
– ClockBoost
TM
feature providing clock multiplication
–
ClockShift
TM
programmable clock phase and delay shifting
Powerful I/O features
–
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG)
PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
– Bidirectional I/O performance (t
CO
+
t
SU
) up to 243 MHz
–
Direct connection from I/O pins to local interconnect providing
fast
t
CO
and
t
SU
times for complex logic
–
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
and 3.3-V devices (see
Table 2)
–
Programmable clamp to V
CCIO
–
Individual tri-state output enable control for each pin
–
Programmable output slew-rate control to reduce switching
noise
–
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), stub-series terminated logic
(SSTL-3), and Gunning transceiver logic (GTL+)
–
Supports hot-socketing operation
–
Pull-up on I/O pins before and during configuration
Table 2. APEX 20K Supply Voltages
Feature
EP20K100
EP20K200
EP20K400
EP20K60E
EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
1.8 V
1.8 V, 2.5 V, 3.3 V
Internal supply voltage (V
CCINT
)
MultiVolt I/O interface voltage
levels (V
CCIO
)
2.5 V
2.5 V, 3.3 V
2
Altera Corporation
Preliminary Information
s
APEX 20K Programmable Logic Device Family Data Sheet
s
s
Advanced interconnect structure
– Four-level hierarchical FastTrack
®
Interconnect structure
providing fast, predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
Advanced packaging options
–
Available in a variety of packages with 144 to 1,020 pins (see
Tables 3
through
6)
–
FineLine BGA
TM
packages maximize board space efficiency
–
SameFrame
TM
pin migration providing migration capability
across device densities and package sizes
Advanced software support
– Software design support and automatic place-and-route
provided by the Altera
®
Quartus
TM
development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
–
Altera MegaCore
TM
functions and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions
–
NativeLink
TM
integration with popular synthesis, simulation,
and timing analysis tools
–
Quartus SignalTap
TM
embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
–
Supports popular revision-control software packages including
PVCS, RCS, and SCCS
Altera Corporation
3
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 3. APEX 20K QFP, BGA & PGA Package Options & I/O Count
Device
144-Pin
TQFP
92
101
92
87
Notes (1), (2), (3)
652-Pin
BGA
655-Pin
PGA
984-Pin
PGA
208-Pin
PQFP
RQFP
151
159
151
143
144
136
120
240-Pin
PQFP
RQFP
183
189
183
175
174
168
152
356-Pin
BGA
204
252
246
273
279
273
EP20K60E
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
376
408
502
488
483
483
716
502
Table 4. APEX 20K FineLine BGA Package Options and I/O Count
Device
EP20K60E
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Notes to tables:
(1)
(2)
(3)
Contact Altera for up-to-date information on package availability.
I/O counts include dedicated input and clock pins.
APEX 20K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, and pin-grid array (PGA)
packages.
All FineLine BGA packages, except the 196-pin and 1,020-pin packages, are footprint-compatible via the
SameFrame feature. Therefore, designers can design a board to support a variety of devices, providing a flexible
migration path across densities and pin counts. Device migration is fully supported by Altera development tools.
See
“SameFrame Pin-Outs” on page 43
for more information.
196-Pin
143
149
143
324-Pin
204
252
246
484-Pin
204
(4)
252
(4)
246
(4)
316
382
376
672-Pin
204
(4)
252
(4)
246
(4)
316
(4)
382
(4)
376
408
502
488
508
508
1,020-Pin
624
716
858
(4)
4
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 5. APEX 20K QFP, BGA & PGA Package Sizes
Feature
Pitch (mm)
Area (mm
2
)
144-Pin TQFP 208-Pin QFP 240-Pin QFP 356-Pin BGA 652-Pin BGA 655-Pin PGA
0.50
484
22
×
22
0.50
936
30.6
×
30.6
0.50
1,197
34.6
×
34.6
1.27
1,225
35
×
35
1.27
2,025
45
×
45
–
3,906
62.5
×
62.5
Length
×
Width
(mm
×
mm)
Table 6. APEX 20K FineLine BGA Package Sizes
Feature
Pitch (mm)
Area
(mm
2
)
Length
×
Width
(mm
×
mm)
196-Pin
1.00
225
15
×
15
324-Pin
1.00
361
19
×
19
484-Pin
1.00
529
23
×
23
672-Pin
1.00
729
27
×
27
1,020-Pin
1.00
1089
33
×
33
General
Description
APEX 20K devices are the first PLDs designed with the MultiCore
architecture, which combines the strengths of LUT-based and product-
term-based devices with an enhanced memory structure. LUT-based logic
provides optimized performance and efficiency for data-path, register-
intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths,
such as complex state machines. LUT- and product-term-based logic
combined with memory functions and a wide variety of MegaCore and
AMPP functions make the APEX 20K architecture uniquely suited for
System-on-a-Programmable-Chip design. Applications historically
requiring a combination of LUT-, product-term-, and memory-based
devices can now be integrated into one APEX 20K device.
APEX 20KE devices are a superset of APEX 20K devices and include
additional features such as advanced I/O standard support, CAM,
additional global clocks, and enhanced ClockLock clock circuitry. In
addition, APEX 20KE devices extend the APEX 20K family to one million
gates. APEX 20KE devices are denoted with an “E” suffix in the device
name (e.g., the EPF20K1000E is an APEX 20KE device).
Table 7
summarizes the features included in APEX 20K and APEX 20KE devices.
Altera Corporation
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