eGaN® FET DATASHEET
EPC2001C
EPC2001C – Enhancement Mode Power Transistor
V
DSS
, 100 V
R
DS(on)
, 7 mW
I
D
, 36 A
NEW PRODUCT
EFFICIENT POWER CONVERSION
HAL
Gallium nitride is grown on silicon wafers and processed using standard CMOS equipment leverag-
ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-
tron mobility and low temperature coefficient allows very low R
DS(on)
, while its lateral device structure
and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are beneficial as well as
those where on-state losses dominate.
EPC2001C eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• High Speed DC-DC conversion
• Class-D Audio
• High Frequency Hard-Switching and
Soft-Switching Circuits
Benefits
• Ultra High Efficiency
• Ultra Low R
DS(on)
• Ultra low Q
G
• Ultra small footprint
Maximum Ratings
V
DS
I
D
V
GS
T
J
T
STG
Drain-to-Source Voltage (Continuous)
Drain-to-Source Voltage (up to 10,000 5ms pulses at 150°C)
Continuous (T
A
= 25˚C,
R
θJA
= 7.3)
Pulsed (25˚C, Tpulse = 300 µs)
Gate-to-Source Voltage
Gate-to-Source Voltage
Operating Temperature
Storage Temperature
100
120
36
150
6
-4
-40 to 150
-40 to 150
V
V
A
V
˚C
Static Characteristics
(T
J
= 25˚C unless otherwise stated)
PARAMETER
BV
DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
V
SD
Drain-to-Source Voltage
Drain Source Leakage
Gate-Source Forward Leakage
Gate-Source Reverse Leakage
Gate Threshold Voltage
Drain-Source On Resistance
Source-Drain Forward Voltage
TEST CONDITIONS
V
GS
= 0 V, I
D
= 300 µA
V
GS
= 0 V, V
DS
= 80 V
V
GS
= 5 V
V
GS
= -4 V
V
DS
= V
GS
, I
D
= 5 mA
V
GS
= 5 V, I
D
= 25 A
I
S
= 0.5 A, V
GS
= 0 V
0.8
MIN
100
100
1
0.1
1.4
5.6
1.7
250
5
0.25
2.5
7
TYP
MAX
UNIT
V
µA
mA
V
mΩ
V
All measurements were done with substrate shorted to source.
Thermal Characteristics
TYP
R
θ
JC
R
θ
JB
R
θ
JA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Board
Thermal Resistance, Junction to Ambient (Note 1)
1
2
54
˚C/W
˚C/W
˚C/W
Note 1: R
θ
JA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
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eGaN® FET DATASHEET
Dynamic Characteristics
(T
J
= 25˚C unless otherwise stated)
PARAMETER
C
ISS
C
OSS
C
RSS
R
G
Q
G
Q
GS
Q
GD
Q
G(TH)
Q
OSS
Q
RR
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge at Threshold
Output Charge
Source-Drain Recovery Charge
V
GS
= 0 V, V
DS
= 50 V
V
DS
= 50 V, I
D
= 25 A
V
DS
= 50 V,
V
GS
= 5 V,
I
D
= 25 A
V
GS
= 0 V, V
DS
= 50 V
TEST CONDITIONS
MIN
TYP
770
430
10
0.3
7.5
2.4
1.2
1.6
31
0
45
2
9
MAX
900
650
15
EPC2001C
UNIT
pF
nC
All measurements were done with substrate shorted to source.
Figure 1: Typical Output Characteristics at 25°C
150
150
Figure 2: Transfer Characteristics
25˚C
125˚C
V
DS
= 3 V
120
120
I
D
– Drain Current (A)
I
D
– Drain Current (A)
3
90
90
60
30
V
GS
= 5 V
V
GS
= 4 V
V
GS
= 3 V
V
GS
= 2 V
60
30
0
0
0.5
V
DS
– Drain-to-Source Voltage (V)
1
1.5
2
2.5
0
0.5
1
1.5
V
GS
– Gate-to-Source Voltage (V)
2
2.5
3
3.5
4
4.5
5
25
Figure 3: R
DS(on)
vs. V
GS
for Various Currents
R
DS(on)
– Drain to Source Resistance (mΩ)
I
D
= 10 A
I
D
= 20 A
I
D
= 40 A
I
D
= 80 A
25
Figure 4: R
DS(on)
vs. V
GS
for Various Temperatures
25˚C
125˚C
I
D
= 25 A
R
DS(on)
– Drain to Source Resistance (mΩ)
20
20
15
15
10
10
5
5
0
2
2.5
V
GS
– Gate-to-Source Voltage (V)
3
3.5
4
4.5
5
0
2
2.5
V
GS
– Gate-to-Source Voltage (V)
3
3.5
4
4.5
5
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eGaN® FET DATASHEET
1.2
1
0.8
0.6
0.4
0.2
0
0.001
EPC2001C
Figure 5b: Capacitance (Log Scale)
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
1
Figure 5a: Capacitance (Linear Scale)
Capacitance (nF)
Capacitance (nF)
0.1
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
0.01
0
20
40
60
80
100
0
20
40
60
80
100
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
Figure 6: Gate Charge
5
4.5
I
D
= 25 A
V
DS
= 50 V
72
60
Figure 7: Reverse Drain-Source Characteristics
25˚C
125˚C
V
GS
– Gate to Source Voltage (V)
3.5
3
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
7
8
I
SD
– Source to Drain Current (A)
4
48
36
24
12
Q
G
– Gate Charge (nC)
0.5
1
1.5
V
SD
– Source-to-Drain Voltage (V)
2
2.5
3
3.5
4
4.5
5
Figure 8: Normalized On Resistance vs. Temperature
2
1.4
I
D
= 25 A
V
GS
= 5 V
Figure 9: Normalized Threshold Voltage vs. Temperature
1.3
I
D
= 5 mA
Normalized On-State Resistance – R
DS(on)
1.8
1.6
1.4
1.2
1
0.8
0.6
Normalized Threshold Voltage
0
25
50
75
100
125
150
1.2
1.1
1
0.9
0.8
0.7
0.6
0
25
50
75
100
125
150
T
J
– Junction Temperature ( ˚C )
T
J
– Junction Temperature ( ˚C )
All measurements were done with substrate shortened to source.
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eGaN® FET DATASHEET
25
EPC2001C
Figure 10: Gate Current
25˚C
125˚C
20
I
G
– Gate Current (mA)
15
10
5
0
0
1
2
3
4
5
6
V
GS
– Gate-to-Source Voltage (V)
Figure 11: Transient Thermal Response Curves
Junction-to-Board
1
Z
θJB
, Normalized Thermal Impedance
Duty Factors:
0.5
0.1
0.05
P
DM
t
p
0.1
T
0.02
0.01
0.01
Single Pulse
0.001
10
-5
Notes:
Duty Factor = t
p
/T
Peak T
J
= P
DM
x Z
θJB
x R
θJB
+ T
B
10
-4
10
-3
10
-2
t
p
- Rectangular Pulse Duration [s]
10
-1
1
10
Junction-to-Case
Z
θC
, Normalized Thermal Impedance
Duty Factors:
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
0.001
Single Pulse
0.0001
10
-5
10
-4
10
-3
10
-2
t
p
- Rectangular Pulse Duration [s]
1
T
P
DM
t
p
Notes:
Duty Factor = t
p
/T
Peak T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-1
1
10
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eGaN® FET DATASHEET
Figure 12: Safe Operating Area
100
EPC2001C
I
D
- Drain Current (A)
10
limited by R
DS(on)
Pulse Width
100 ms
10 ms
1 ms
100 us
1
0.1
0.1
1
10
100
V
DS
- Drain-Source Voltage (V)
T
J
= Max Rated, T
C
= +25°C, Single Pulse
TAPE AND REEL CONFIGURATION
4mm pitch, 12mm wide tape on 7” reel
7” reel
b
d
e
f
g
Loaded Tape Feed Direction
Die
orientation
dot
a
c
Gate
solder bar is
under this
corner
EPC2001C (note 1)
Dimension (mm)
target
min
max
Die is placed into pocket
solder bar side down
(face side down)
a
b
c (note 2)
d
e
f (note 2)
g
12.0
1.75
5.50
4.00
4.00
2.00
1.5
11.7
1.65
5.45
3.90
3.90
1.95
1.5
12.3
1.85
5.55
4.10
4.10
2.05
1.6
Note 1:
Note 2:
MSL1 (moisture sensitivity level 1) classi ed according to IPC/JEDEC industry standard.
Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
2001
YYYY
Die orientation dot
Gate Pad solder bar
is under this corner
ZZZZ
Part
Number
EPC2001C
Laser Markings
Part #
Marking Line 1
2001
Lot_Date Code
Marking line 2
YYYY
Lot_Date Code
Marking Line 3
ZZZZ
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| COPYRIGHT 2014 |
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