EVB72005
315MHz FSK/ASK Transmitter
Evaluation Board Description
Features
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Fully integrated PLL-stabilized VCO
Frequency range from 290 MHz to 350 MHz
Single-ended RF output
FSK through crystal pulling allows modulation
from DC to 40 kbit/s
High FSK deviation possible for wideband data
transmission
ASK achieved by on/off keying of internal
power amplifier up to 40 kbit/s
Wide power supply range from 1.95 V to 5.5 V
Very low standby current
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On-chip low voltage detector
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High over-all frequency accuracy
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FSK deviation and center frequency independ-
ently adjustable
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Adjustable output power range from
-12 dBm to +11 dBm (at connector board)
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Adjustable effective radiated power (ERP) range
from -31 dBm to -8 dBm (at antenna board)
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Adjustable current consumption from
3.2 mA to 10.3 mA
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Conforms to FCC part 15 and similar standards
Ordering Information
Part No. (see paragraph 6)
EVB72005-315-FSK-A
EVB72005-315-FSK-C (on request)
Note 1:
EVB default population is FSK, ASK modifications according to section 3.1 and 4.1.
Note 2:
EVB72005 is applicable for devices TH72005, TH72001 and TH72002.
Application Examples
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General digital data transmission
Tire Pressure Monitoring Systems (TPMS)
Remote Keyless Entry (RKE)
Wireless access control
Alarm and security systems
Garage door openers
Remote Controls
Home and building automation
Low-power telemetry systems
Evaluation Board Example
General Description
The TH72005 evaluation board is designed to demonstrate the performance of the transmitter IC with an
on-board loop antenna. This board allows the user to setup an RF transmitter very easily. Alternatively a
50 Ohm connector board can be requested.
39012 72005 01
Rev. 007
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EVB Description
June/07
EVB72005
315MHz FSK/ASK Transmitter
Evaluation Board Description
Document Content
1
Theory of Operation ...................................................................................................3
1.1
1.2
General............................................................................................................................. 3
Block Diagram .................................................................................................................. 3
2
Functional Description ..............................................................................................3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Crystal Oscillator .............................................................................................................. 3
FSK Modulation ................................................................................................................ 4
Crystal Pulling................................................................................................................... 4
ASK Modulation................................................................................................................ 5
Output Power Selection.................................................................................................... 5
Lock Detection.................................................................................................................. 5
Low Voltage Detection...................................................................................................... 5
Mode Control Logic .......................................................................................................... 6
Timing Diagrams .............................................................................................................. 6
3
Antenna Board Circuit Diagram................................................................................7
3.1
3.2
3.3
Board Component Values to Fig. 6 .................................................................................. 7
Antenna Board PCB Top View ......................................................................................... 8
Board Connection............................................................................................................. 8
4
50
Ω
Connector Board Circuit Diagram.....................................................................9
4.1
4.2
4.3
Board Component Values to Fig. 7 .................................................................................. 9
50
Ω
Connector Board PCB Top View ............................................................................ 10
Board Connection........................................................................................................... 10
5
Evaluation Board Layouts .......................................................................................11
5.1
5.2
5.3
Antenna Board................................................................................................................ 11
PCB Loop Antenna Dimensions ..................................................................................... 11
Connector Board ............................................................................................................ 12
6
7
Board Variants..........................................................................................................12
Package Description ................................................................................................13
7.1
7.2
Soldering Information ..................................................................................................... 13
Recommended PCB Footprints ...................................................................................... 13
8
Disclaimer .................................................................................................................14
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Rev. 007
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EVB Description
June/07
EVB72005
315MHz FSK/ASK Transmitter
Evaluation Board Description
1 Theory of Operation
1.1
General
As depicted in Fig.1, the TH72005 transmitter consists of a fully integrated voltage-controlled oscillator
(VCO), a divide-by-32 divider (div32), a phase-frequency detector (PFD) and a charge pump (CP). An inter-
nal loop filter determines the dynamic behavior of the PLL and suppresses reference spurious signals. A
Colpitts crystal oscillator (XOSC) is used as the reference oscillator of a phase-locked loop (PLL) synthe-
sizer. The VCO’s output signal feeds the power amplifier (PA). The RF signal power P
out
can be adjusted in
four steps from P
out
= –12 dBm to +11 dBm, either by changing the value of resistor RPS or by varying the
voltage V
PS
at pin PSEL. The open-collector output (OUT) can be used either to directly drive a loop antenna
or to be matched to a 50Ohm load. Bandgap biasing ensures stable operation of the IC at a power supply
range of 1.95 V to 5.5 V.
1.2
Block Diagram
RPS
VCC
PSEL
ASKDTA
10
ENTX
6
1
8
5
PLL
mode
control
32
PA
OUT
antenna
matching
network
ROI
4
XTAL
FSKSW
CX2
CX1
3
2
FSKDTA
PFD
XOSC
XBUF
CP
VCO
low
voltage
detector
7
VEE
9
VEE
Fig. 1:
Block diagram with external components
2 Functional Description
2.1
Crystal Oscillator
A Colpitts crystal oscillator with integrated functional capacitors is used as the reference oscillator for the PLL
synthesizer. The equivalent input capacitance CRO offered by the crystal oscillator input pin ROI is about
18pF. The crystal oscillator is provided with an amplitude control loop in order to have a very stable fre-
quency over the specified supply voltage and temperature range in combination with a short start-up time.
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Rev. 007
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EVB Description
June/07
EVB72005
315MHz FSK/ASK Transmitter
Evaluation Board Description
2.2 FSK Modulation
FSK modulation can be achieved by pulling the
crystal oscillator frequency. A CMOS-
compatible data stream applied at the pin
FSKDTA digitally modulates the XOSC via an
integrated NMOS switch. Two external pulling
capacitors CX1 and CX2 allow the FSK devia-
tion
Δf
and the center frequency f
c
to be ad-
justed independently. At FSKDTA = 0, CX2 is
connected in parallel to CX1 leading to the low-
frequency component of the FSK spectrum
(f
min
); while at FSKDTA = 1, CX2 is deactivated
and the XOSC is set to its high frequency f
max
.
An external reference signal can be directly AC-
coupled to the reference oscillator input pin
ROI. Then the transmitter is used without a
crystal. Now the reference signal sets the car-
rier frequency and may also contain the FSK (or
FM) modulation.
Fig. 2:
Crystal pulling circuitry
ROI
VCC
XTAL
FSKSW
CX2
CX1
VEE
FSKDTA
0
1
Description
fmin= fc -
Δf
(FSK switch is closed)
fmax= fc +
Δf
(FSK switch is open)
2.3 Crystal Pulling
A crystal is tuned by the manufacturer to the
required oscillation frequency f
0
at a given load
capacitance CL and within the specified calibra-
tion tolerance. The only way to pull the oscilla-
tion frequency is to vary the effective load ca-
pacitance CL
eff
seen by the crystal.
Figure 3 shows the oscillation frequency of a
crystal as a function of the effective load ca-
pacitance. This capacitance changes in accor-
dance with the logic level of FSKDTA around
the specified load capacitance. The figure illus-
trates the relationship between the external
pulling capacitors and the frequency deviation.
It can also be seen that the pulling sensitivity
increases with the reduction of CL. Therefore,
applications with a high frequency deviation
require a low load capacitance. For narrow
band FSK applications, a higher load capaci-
tance could be chosen in order to reduce the
frequency drift caused by the tolerances of the
chip and the external pulling capacitors.
f
XTAL
L1
f
max
C1
R1
C0
CL
eff
f
c
f
min
CX1 CRO
CX1+CRO
CL
(CX1+CX2) CRO
CX1+CX2+CRO
CL
eff
Fig. 3:
Crystal pulling characteristic
For ASK applications CX2 can be omitted. Then CX1 has to be adjusted for center frequency.
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Rev. 007
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EVB Description
June/07
EVB72005
315MHz FSK/ASK Transmitter
Evaluation Board Description
2.4
ASK Modulation
ASKDTA
0
1
Description
Power amplifier is turned off
Power amplifier is turned on (according
to the selected output power step)
The PLL transmitter can be ASK-modulated by
applying a data stream directly at the pin
ASKDTA. This turns the internal current
sources of the power amplifier on and off and
therefore leads to an ASK signal at the output.
2.5
Output Power Selection
The transmitter is provided with an output power selection feature. There are four predefined output power
steps and one off-step accessible via the power selection pin PSEL. A digital power step adjustment was
chosen because of its high accuracy and stability. The number of steps and the step sizes as well as the
corresponding power levels are selected to cover a wide spectrum of different applications.
The implementation of the output power control
logic is shown in figure 4. There are two
matched current sources with an amount of
about 8 µA. One current source is directly ap-
plied to the PSEL pin. The other current source
is used for the generation of reference voltages
with a resistor ladder. These reference voltages
are defining the thresholds between the power
steps. The four comparators deliver thermome-
ter-coded control signals depending on the
voltage level at the pin PSEL. In order to have a
certain amount of ripple tolerance in a noisy
environment the comparators are provided with
a little hysteresis of about 20 mV. With these
control signals, weighted current sources of the
power amplifier are switched on or off to set the
desired output power level (Digitally Controlled
Current Source). The LOCK, ASK signal and
the output of the low voltage detector are gating
this current source.
RPS
PSEL
&
ASKDTA
&
&
&
&
OUT
Fig. 4:
Block diagram of output power control circuitry
There are two ways to select the desired output power step. First by applying a DC voltage at the pin PSEL,
then this voltage directly selects the desired output power step. This kind of power selection can be used if
the transmission power must be changed during operation. For a fixed-power application a resistor can be
used which is connected from the PSEL pin to ground. The voltage drop across this resistor selects the de-
sired output power level. For fixed-power applications at the highest power step this resistor can be omitted.
The pin PSEL is in a high impedance state during the “TX standby” mode.
2.6
Lock Detection
The lock detection circuitry turns on the power amplifier only after PLL lock. This prevents from unwanted
emission of the transmitter if the PLL is unlocked.
2.7
Low Voltage Detection
The supply voltage is sensed by a low voltage detect circuitry. The power amplifier is turned off if the supply
voltage drops below a value of about 1.85 V. This is done in order to prevent unwanted emission of the
transmitter if the supply voltage is too low.
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Rev. 007
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EVB Description
June/07
嵌入式系统
