F71889
F71889
Super Hardware Monitor + LPC I/O
Release Date: April, 2010
Version: V0.28P
April, 2010
V0.28P
F71889
F71889 Datasheet Revision History
Version
V0.10P
V0.11P
V0.12P
V0.13P
V0.14P
V0.15P
V0.16P
Date
2007/11/23
2008/1/16
2008/1/29
2008/7/2
2008/8/15
2008/10/22
2008/11/28
Page
-
-
-
-
-
-
6,8
118
38
118
6
V0.18P
2009/1/5
83
92
118
-
79
V0.19P
2009/1/6
83
85
91
92
5
Preliminary Version.
Modify Pin25/26 description.
Add function description and register description
Add new functions by power on strapping
Add application circuit and VID/GPIO new functions
Modify typo.
Modify the description of pin99, pin122
Update application circuit page 1.
Add VREF timing sequence sketch
Update application circuit page 1.
Rename pin99 AVCC to AVSB
Modify the description of Index 27h bit2
Remove Index F0h Clock Select Register
Update application circuit page 1. (Rename pin99)
Modify typo. (Blue Color) on page 8, 9, 10, 11, 12, 13, 14.
Modify KBC device config. register table (Blue Color)
Modify ROM address select register bit1-0 description.
Modify Wakeup control register bit2-1 description.
Modify default value of Index70/72 register.
Add “Powered by VSB3V” description on all GPIO register.
Revise pin configuration. The details can be referred in
P.13
Add IBX SCL/SDA pin description in pin 43, 44. Only
description updated, no function change
Move the description of VREF to P.75 from P.37, and
modify the contents
CR01, bit 5,TSI_EN, cleared by LRESET#
CR0A, bit 4,SST_EN, cleared by LRESET#
Change SPI clock default to 16.7MHz
Create a new bit “7” in Register 0x20 to choose the
81
conversion rate of the temperature from the digital
interface
85
Create a new bit “7” in Register 0x2C to choose GPIO1x
and GPIO2x clear condition
April, 2010
V0.28P
Revision History
V0.17P
2008/12/3
13
38, 76
V0.20P (Start
from Version
E)
2009/2/5
47
48
74
F71889
Create a new bit ”5” in Register 0x2D to set VREF_VSYS
and VREF_VTT status in the S3 state
V0.21P (Start
from Version
F)
2009/3/18
3
Rename:
VREF_VTT to VREF3, VREF_VSYS to VREF2,
VREF_VRAM to VREF1
Revise Pin Configuration
5
Pin 85: VREF_VTT
Pin 86: VREF_VSYS
Pin 87: VREF_VDRAM
Pin-out rename:
Pin 85: VREF_VTT
Pin 86: VREF_VSYS
14
Pin 87: VREF_VDRAM
VREF3
VREF2
VREF1
VREF3
VREF2
VREF1
Add dexcriptions for Pin84~87
Add pin 80 PWROK falling condition description
Modify pin 81 RSMRST# falling condition to VSB3V under
2.95V
16
40
41
42
51
Revise typo: PWMDUTY
Remove Fig. 7-5/7-6
Remove Fig. 7-7/7-8
FAN60_100
Revise Fig. 7-5, (original Fig. 7-10)
Revise Fig. 7-6, (original Fig. 7-11)
Rename V1~V6 to VIN1~VIN6
Revise CR20h, 27h, 28h to Reserved
Typo revised and pin-out rename:
The F71889 also supports 4 3 output voltages for VREF,
VRAM, VSYS and VTT.VREF1~3. The output is generated
Below is the timing sequence between
VFEF_VRAM/VREF_VSYS/VREF_VTT VREF1~3pins:
Revise VREF1~3 timing chart
76
79
Revise Section 7.11 SST Fuction description
Register 0xF0: Rename VREF_VTT to VREF3
83
Register 0xF1: Rename VREF_VSYS to VREF2
Register 0xF2: Rename VREF_VRAM to VREF1
Swap CR0x2C bit 6 and 4
88
Create a new bit ”6” in Register 0x2D to set VREF1~3 are
reset or not in the S3/S4/S5 state
April, 2010
V0.28P
F71889
Revise Register0x2D bit5 description: revise the reference
voltage output definition to VREF1~3
Register 0xF0: Rename VREF_VTT to VREF3 in the
relative description
115
Register 0xF1: Rename VREF_VSYS to VREF2 in the
relative description
Register 0xF2: Rename VREF_VRAM to VREF1 in the
relative description
Revise Register 0xF3 bit2~0 description: revise the
116
reference voltage output definition to VREF1~3
Revise Register 0xFF bit0 description: revise the reference
voltage output definition to VREF1~3
121
16
0.22P
2009/05/04
51
55-57
73
0.23P
2009/05/12
66
93
92
Revise Application circuit
Remove FDC, UART, Parallel port descriptions
Revise CR20h, 27h, 28h typo
Revise VREF timing chart
Revise Typo: (8) CTRL + Alt + user define key Space
Revise CR2Dh bit 6 description
Revise CRF6h bit 3 description
Revise CRF4h bit 5 description
0.24P
2009/5/19
10: DUAL_GATE_N tri-state in S5 state.
01: DUAL_GATE_N output low in S5 state.
Made Corrections & Clarification
0.25P
2009/8/3
Update Power Type for Pin 72
Revise Application circuit (Sheet 1)
Made Corrections & Clarification
Update Fan 1~3 Related Setting Index A6~A9, B6~B9, and
C6~C9
0.26P
2009/8/24
BUSIN Register Index 04h
GPIO0 and GPIO1 Pin Status Index F2h and E2h
TSI and SMBus Related Register Index E0h~EDh
Update Application Circuit (Add Intel IBX)
Made Corrections & Clarification
0.27P
2009
Update Electrical Characteristics
GPIO0 Drive Enable Register
⎯
Index F3h, bit 3
0.28P
2010/4/19
Made Corrections & Clarification
April, 2010
V0.28P
F71889
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from
such improper use or sales.
April, 2010
V0.28P
