November 1998
FDG6321C
Dual N & P Channel Digital FET
General Description
These dual N & P-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage
applications as a replacement for bipolar digital transistors and
small signal MOSFETS. Since bias resistors are not required,
this dual digital FET can replace several different digital
transistors, with different bias resistor values.
Features
N-Ch 0.50 A, 25 V, R
DS(ON)
= 0.45
Ω
@ V
GS
= 4.5V.
R
DS(ON)
= 0.60
Ω
@ V
GS
= 2.7 V.
P-Ch -0.41 A, -25 V,R
DS(ON)
= 1.1
Ω
@ V
GS
= -4.5V.
R
DS(ON)
= 1.5
Ω
@ V
GS
= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits(V
GS(th)
< 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
SC70-6
SOT-23
SuperSOT
TM
-6
SOT-8
SO-8
SOIC-14
G2
D1
S2
1
6
.21
2
5
SC70-6
S1
D2
G1
3
4
Absolute Maximum Ratings
Symbol
V
DS
S
V
GSS
I
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current
T
A
= 25
o
C unless otherwise noted
N-Channel
25
8
0.5
1.5
(Note 1)
P-Channel
-25
-8
-0.41
-1.2
0.3
-55 to 150
6
Units
V
V
A
- Continuous
- Pulsed
P
D
T
J
,T
STG
ESD
Maximum Power Dissipation
W
°C
kV
Operating and Storage Temperature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
THERMAL CHARACTERISTICS
R
θJA
(Note 1)
415
°C/W
© 1998 Fairchild Semiconductor Corporation
FDG6321C Rev. D
Electrical Characteristics
(
T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Type
N-Ch
P-Ch
o
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, I
D
= -250 µA
I
D
= 250 µA, Referenced to 25 C
I
D
= -250 µA, Referenced to 25
o
C
I
DSS
I
GSS
I
GSS
Zero Gate Voltage Drain Current
V
DS
= 20 V, V
GS
= 0 V
T
J
= 55°C
Gate - Body Leakage Current
V
DS
= -20 V, V
GS
= 0 V
T
J
= 55°C
Gate - Body Leakage Current
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= V
GS
, I
D
= -250 µA
I
D
= 250 µA, Referenced to 25 C
I
D
= -250 µA, Referenced to 25
o
C
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 4.5 V, I
D
= 0.5 A
T
J
=125°C
V
GS
= 2.7 V, I
D
= 0.2 A
V
GS
= -4.5 V, I
D
= -0.41 A
T
J
=125°C
V
GS
= -2.7 V, I
D
= -0.25 A
I
D(ON)
g
FS
On-State Drain Current
V
GS
= 4.5 V, V
DS
= 5 V
V
GS
= -4.5 V, V
DS
= -5 V
Forward Transconductance
V
DS
= 5 V, I
D
= 0.5 A
V
DS
= -5 V, I
D
= -0.41 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
N-Channel
V
DS
= 10 V, V
GS
= 0 V,
Output Capacitance
Reverse Transfer Capacitance
f = 1.0 MHz
P-Channel
V
DS
= -10 V, V
GS
= 0V,
f = 1.0 MHz
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
50
62
28
34
9
10
pF
N-Ch
P-Ch
N-Ch
P-Ch
0.5
-0.41
1.45
0.9
S
P-Ch
o
25
-25
26
-22
1
10
V
mV/
o
C
∆
BV
DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
N-Ch
P-Ch
N-Ch
µA
P-Ch
-1
-10
µA
N-Ch
P-Ch
100
-100
nA
nA
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
0.65
-0.65
0.8
-0.82
-2.6
2.1
0.34
0.55
0.44
0.85
1.2
1.15
1.5
-1.5
V
mV/
o
C
∆
V
GS(th)
/
∆
T
J
Gate Threshold Voltage Temp. Coefficient
0.45
0.72
0.6
1.1
1.8
1.5
Ω
A
FDG6321C Rev. D
Electrical Characteristics
(continued)
SWITCHING CHARACTERISTICS
(Note 2)
Symbol
t
D(on)
t
r
Parameter
Turn - On Delay Time
Conditions
N-Channel
V
DD
= 5 V, I
D
= 0.5 A,
Turn - On Rise Time
V
GS
= 4.5 V, R
GEN
= 50
Ω
P-Channel
V
DD
= -5 V, I
D
= -0.5 A,
t
f
Turn - Off Fall Time
V
GS
= -4.5 V, R
GEN
= 50
Ω
N-Channel
V
DS
= 5 V, I
D
= 0.5 A,
Q
gs
Q
gd
Gate-Source Charge
V
GS
= 4.5 V
P- Channel
Gate-Drain Charge
V
DS
= -5 V, I
D
= -0.41 A,
V
GS
= -4.5 V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Maximum Continuous Drain-Source Diode Forward Current
N-Ch
P-Ch
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 0.5 A
V
GS
= 0 V, I
S
= -0.5 A
(Note 2)
(Note 2)
Type
N-Ch
P-Ch
N-Ch
P-Ch
Min
Typ
3
7
8.5
8
17
55
13
35
1.64
1.1
0.38
0.31
0.45
0.29
Max
6
15
18
16
30
80
25
60
2.3
1.5
Units
nS
nS
t
D(off)
Turn - Off Delay Time
N-Ch
P-Ch
N-Ch
P-Ch
nS
nS
Q
g
Total Gate Charge
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
nC
nC
nC
0.25
-0.25
0.8
-0.85
1.2
-1.2
A
N-Ch
P-Ch
V
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design. R
θ
JA
= 415
O
C/W on minimum mounting pad on FR-4 board in still air.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDG6321C Rev. D
Typical Electrical Characteristics: N-Channel
DRAIN-SOURCE ON-RESISTANCE
1.5
I
D
, DRAIN-SOURCE CURRENT (A)
V
GS
= 4.5V
3.0V
2.7V
2
2.5V
R
DS(ON)
, NORMALIZED
1.2
2.0V
V
GS
= 2.0V
1.5
0.9
2.5V
2.7V
1
3.0V
3.5V
4.5V
0.6
1.5V
0.3
0
0.5
0
0.5
1
1.5
2
2.5
3
V
DS
, DRAIN-SOURCE VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
DRAIN-SOURCE ON-RESISTANCE
R
DS(ON)
, NORMALIZED
2
I
D
= 0.5A
1.4
R
DS(on)
, ON-RESISTANCE (OHM)
I
D
= 0.3A
1.6
V
GS
= 4.5 V
1.2
1.2
1
0.8
T
A
= 125°C
0.8
0.4
T
A
= 25°C
0
1
1.5
2
2.5
3
3.5
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
4.5
5
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
V
DS
= 5.0V
I
D
, DRAIN CURRENT (A)
0.8
T = -55°C
J
25°C
125°C
I
S
, REVERSE DRAIN CURRENT (A)
1
1
V
GS
= 0V
T
J
= 125°C
25°C
-55°C
0.1
0.6
0.01
0.4
0.001
0.2
0
0.0001
0
0.5
1
1.5
2
2.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDG6321C Rev. D
Typical Electrical Characteristics: N-Channel
(continued)
5
V
GS
, GATE-SOURCE VOLTAGE (V)
200
I
D
= 0.5A
4
CAPACITANCE (pF)
V
DS
= 5V
10V
15V
70
Ciss
30
3
Coss
2
10
1
3
0.1
f = 1 MHz
V
GS
= 0V
0
0.4
0.8
1.2
1.6
2
0.3
1
2
5
10
C rss
0
Q
g
, GATE CHARGE (nC)
25
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
3
IT
LIM
50
I
D
, DRAIN CURRENT (A)
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1
s
POWER (W)
N)
(O
DS
R
1m
s
10m
s
10
0m
40
SINGLE PULSE
R
θ
JA
=415°C/W
T
A
= 25°C
30
1s
V
GS
= 4.5V
SINGLE PULSE
R
θ
JA
= 415 °C/W
T
A
= 25°C
1
V
DS
10
s
DC
20
10
2
5
10
25
40
0
0.0001
0.001
0.01
0.1
1
10
200
, DRAI N-SOURCE VOLTAGE (V)
SINGLE PULSE TIME (SEC)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
FDG6321C Rev. D
