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FDZ197PZ

EEPROM 512K 64K X 8 2.5V HI-SPEED SER EE IND

器件类别：分立半导体    晶体管   

厂商名称：Fairchild

厂商官网：http://www.fairchildsemi.com/

器件标准：

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器件参数
参数名称
属性值
Brand Name
Fairchild Semiconductor
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Fairchild
零件包装代码
CSP
包装说明
GRID ARRAY, R-PBGA-B6
针数
6
制造商包装代码
6 BALL WLCSP, 2X3 ARRAY, 0.5MM PITCH, 300UM BALL
Reach Compliance Code
compliant
ECCN代码
EAR99
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
20 V
最大漏极电流 (Abs) (ID)
3.8 A
最大漏极电流 (ID)
3.8 A
最大漏源导通电阻
0.071 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)
225 pF
JESD-30 代码
R-PBGA-B6
JESD-609代码
e1
湿度敏感等级
1
元件数量
1
端子数量
6
工作模式
ENHANCEMENT MODE
最高工作温度
150 °C
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
GRID ARRAY
峰值回流温度（摄氏度）
260
极性/信道类型
P-CHANNEL
最大功率耗散 (Abs)
1.9 W
认证状态
Not Qualified
表面贴装
YES
端子面层
Tin/Silver/Copper (Sn/Ag/Cu)
端子形式
BALL
端子位置
BOTTOM
处于峰值回流温度下的最长时间
NOT SPECIFIED
晶体管应用
SWITCHING
晶体管元件材料
SILICON
文档预览
Is Now Part of
To learn more about ON Semiconductor, please visit our website at
www.onsemi.com
Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
product management systems do not have the ability to manage part nomenclature that utilizes an underscore
(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at
www.onsemi.com.
Please
email any questions regarding the system integration to
Fairchild_questions@onsemi.com.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
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FDZ197PZ P-Channel 1.5 V Specified PowerTrench
®
Thin WL-CSP MOSFET
December 2014
FDZ197PZ
P-Channel 1.5 V Specified PowerTrench
®
Thin WL-CSP MOSFET
-20 V, -3.8 A, 64 mΩ
Features
Max r
DS(on)
= 64 mΩ at V
GS
= -4.5 V, I
D
= -2.0 A
Max r
DS(on)
= 71 mΩ at V
GS
= -2.5 V, I
D
= -2.0 A
Max r
DS(on)
= 79 mΩ at V
GS
= -1.8 V, I
D
= -1.0 A
Max r
DS(on)
= 95 mΩ at V
GS
= -1.5 V, I
D
= -1.0 A
Occupies only 1.5 mm
2
of PCB area.Less than 50% of the
area of 2 x 2 BGA
Ultra-thin package: less than 0.65 mm height when mounted
to PCB
HBM ESD protection level > 4400V (Note3)
RoHS Compliant
General Description
Designed on Fairchild's advanced 1.5 V PowerTrench
®
process
with state of the art "fine pitch" WLCSP packaging process, the
FDZ197PZ minimizes both PCB space and r
DS(on)
. This
advanced WLCSP MOSFET embodies a breakthrough in
packaging technology which enables the device to combine
excellent thermal transfer characteristics, ultra-low profile
packaging, low gate charge, and low r
DS(on)
.
Applications
Battery management
Load switch
Battery protection
PIN1
S
S
D
D
S
G
TOP
WL-CSP 1x1.5 Thin
BOTTOM
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted
Symbol
V
DS
V
GS
I
D
P
D
T
J
, T
STG
Drain to Source Voltage
Gate to Source Voltage
-Continuous
-Pulsed
Power Dissipation
Power Dissipation
T
A
= 25°C
T
A
= 25°C
(Note 1a)
(Note 1b)
T
A
= 25°C
(Note 1a)
Parameter
Ratings
-20
±8
-3.8
-15
1.9
0.9
-55 to +150
Units
V
V
A
W
°C
Operating and Storage Junction Temperature Range
Thermal Characteristics
R
θJA
R
θJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
(Note 1a)
(Note 1b)
65
133
°C/W
Package Marking and Ordering Information
Device Marking
7
Device
FDZ197PZ
Package
WL-CSP 1x1.5 Thin
Reel Size
7”
Tape Width
8 mm
Quantity
5000 units
©2009 Fairchild Semiconductor Corporation
FDZ197PZ Rev.C3
1
www.fairchildsemi.com
FDZ197PZ P-Channel 1.5 V Specified PowerTrench
®
Thin WL-CSP MOSFET
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
∆BV
DSS
∆T
J
I
DSS
I
GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
D
= -250
µA,
V
GS
= 0 V
I
D
= -250
µA,
referenced to 25 °C
V
DS
= -16 V, V
GS
= 0 V
V
GS
= ±8 V, V
DS
= 0 V
-20
-10
-1
±10
V
mV/°C
µA
µA
On Characteristics
V
GS(th)
∆V
GS(th)
∆T
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V
GS
= V
DS
, I
D
= -250
µA
I
D
= -250
µA,
referenced to 25 °C
V
GS
= -4.5 V, I
D
= -2.0 A
V
GS
= -2.5 V, I
D
= -2.0 A
r
DS(on)
Static Drain to Source On Resistance
V
GS
= -1.8 V, I
D
= -1.0 A
V
GS
= -1.5 V, I
D
= -1.0 A
V
GS
= -4.5 V, I
D
= -2.0 A,
T
J
=125 °C
g
FS
Forward Transconductance
V
DD
= -5 V, I
D
= -3.8 A
-0.4
-0.5
2.7
46
53
59
68
54
21
64
71
79
95
84
S
mΩ
-1.0
V
mV/°C
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= -10 V, V
GS
= 0 V,
f = 1 MHz
1180
190
160
1570
255
225
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
GS
= 0V to -4.5V
V
DD
= -10 V,
I
D
= -3.8 A
V
DD
= -10 V, I
D
= -3.8 A,
V
GS
= -4.5 V, R
GEN
= 6
Ω
5.8
5.9
311
280
18
1.5
4.7
12
12
498
448
25
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics
V
SD
t
rr
Q
rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V
GS
= 0 V, I
S
= -1.1 A
(Note 2)
-0.6
194
344
-1.2
310
550
V
ns
nC
I
F
= -3.8 A, di/dt = 100 A/µs
Notes:
1. R
θJA
is determined with the device mounted on a 1 in
2
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJC
is guaranteed by design while R
θCA
is determined by
the user's board design.
a. 65 °C/W when mounted on
a 1 in
2
pad of 2 oz copper.
b. 133 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection ESD. No gate overvoltage rating is implied.
©2009 Fairchild Semiconductor Corporation
FDZ197PZ Rev.C3
2
www.fairchildsemi.com
FDZ197PZ P-Channel 1.5 V Specified PowerTrench
®
Thin WL-CSP MOSFET
Typical Characteristics
T
J
= 25 °C unless otherwise noted
15
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
2.5
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
-I
D
,
DRAIN CURRENT (A)
12
V
GS
= -4.5 V
2.0
V
GS
= -1.5 V
9
6
3
V
GS
= -3 V
V
GS
= -2.5 V
V
GS
= -1.8 V
V
GS
= -1.5 V
1.5
V
GS
= -1.8 V
V
GS
= -2.5 V
1.0
V
GS
= -3 V
V
GS
= -4.5 V
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
-V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
0.5
0
3
6
9
12
15
-I
D
,
DRAIN CURRENT (A)
Figure 1. On-Region Characteristics
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
150
SOURCE ON-RESISTANCE
(
m
Ω
)
1.4
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
I
D
= -2 A
V
GS
= -4.5 V
I
D
= -2 A
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
1.2
r
DS(on),
DRAIN TO
120
1.0
90
T
J
= 125
o
C
0.8
60
T
J
= 25
o
C
0.6
-75
-50
-25
0
25 50 75 100 125 150
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
30
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On- Resistance
vs Junction Temperature
15
-I
S
, REVERSE DRAIN CURRENT (A)
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
Figure 4. On-Resistance vs Gate to
Source Voltage
20
10
V
GS
= 0 V
-I
D
, DRAIN CURRENT (A)
12
V
DS
= -5 V
1
T
J
= 150
o
C
9
6
T
J
= 150
o
C
T
J
= 25
o
C
0.1
T
J
= 25
o
C
3
T
J
= -55
o
C
0.01
T
J
= -55
o
C
0
0.0
0.5
1.0
1.5
2.0
0.001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-V
GS
, GATE TO SOURCE VOLTAGE (V)
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
©2009 Fairchild Semiconductor Corporation
FDZ197PZ Rev.C3
3
www.fairchildsemi.com
FDZ197PZ P-Channel 1.5 V Specified PowerTrench
®
Thin WL-CSP MOSFET
Typical Characteristics
T
J
= 25 °C unless otherwise noted
-V
GS
, GATE TO SOURCE VOLTAGE (V)
4.5
I
D
= -3.8 A
CAPACITANCE (pF)
V
DD
= -8 V
3000
3.0
V
DD
= -10 V
1000
C
iss
1.5
V
DD
= -12 V
C
oss
f = 1 MHz
V
GS
= 0 V
C
rss
0.0
0
3
6
9
12
15
18
Q
g
, GATE CHARGE (nC)
100
0.1
1
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
20
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs Drain
to Source Voltage
20
10
100
µ
s
-I
D
, DRAIN CURRENT (A)
10
-I
AS
, AVALANCHE CURRENT (A)
1 ms
T
J
= 25
o
C
1
10 ms
THIS AREA IS
LIMITED BY r
DS(on)
1
T
J
= 125
o
C
0.1
SINGLE PULSE
T
J
= MAX RATED
R
θ
JA
= 133
o
C/W
T
A
= 25
o
C
100 ms
1s
DC
0.1
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
50
t
AV
, TIME IN AVALANCHE (ms)
-V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Unclamped Inductive
Switching Capability
10
-I
g
,
GATE LEAKAGE CURRENT (A)
-2
Figure 10. Forward Bias Safe
Operating Area
200
10
10
10
10
10
10
10
-3
V
GS
= 0 V
P
(
PK
)
,
PEAK TRANSIENT POWER (W)
100
SINGLE PULSE
R
θ
JA
= 133
o
C/W
T
A
= 25
o
C
-4
-5
T
J
= 125
o
C
10
-6
-7
T
J
= 25
o
C
-8
1
0.5
-4
10
10
-3
-9
0
3
6
9
12
15
10
-2
10
-1
1
10
100
1000
-V
GS,
GATE TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (sec)
Figure 11. Gate Leakage Current vs
Gate to Source Voltage
Figure 12. Single Pulse Maximum
Power Dissipation
©2009 Fairchild Semiconductor Corporation
FDZ197PZ Rev.C3
4
www.fairchildsemi.com
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器件捷径:
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