FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
1.0 Features
• Extremely flexible and low-jitter phase-locked loop (PLL)
frequency synthesis
• No external loop filter components needed
• 150MHz CMOS or 340MHz PECL outputs
• Completely configurable via I
2
C™-bus
• Up to four FS7140 or FS7145 can be used on a single
I
2
C-bus
• 3.3V operation
• Independent on-chip crystal oscillator and external
reference input
• Very low "cumulative" jitter
Data Sheet
2.0 Description
The FS7140 / FS7145 is a monolithic CMOS clock gen-
erator/regenerator IC designed to minimize cost and
component count in a variety of electronic systems. Via the I
2
C-
bus interface, the FS714x can be adapted to many clock
generation requirements.
The length of the reference and feedback dividers, their fine
granularity, and the flexibility of the post divider make the
FS714x the most flexible stand-alone phase-locked loop (PLL)
clock generator available.
3.0 Applications
SCL
SDA
ADDR0
VSS
XIN
XOUT
ADDR1
VDD
1
2
3
16
15
14
CLKN
CLKP
VDD
n/c
REF
VSS
n/c
IPRG
SCL
SDA
ADDR0
VSS
XIN
XOUT
ADDR1
VDD
1
2
3
16
15
14
CLKN
CLKP
VDD
SYNC
REF
VSS
n/c
IPRG
4
5
6
7
8
13
12
11
10
9
4
5
6
7
8
13
12
11
10
9
•
•
•
•
Precision frequency synthesis
Low-frequency clock multiplication
Video line-locked clock generation
Laser beam printers (FS7145)
Figure 1: Pin Configuration:
16-pin (0.150”) SOIC, 16-pin (5.3mm) SSOP
SYNC
(FS7145 only)
XIN
XOUT
Crystal
Oscillator
Reference
Divider
(N
R
)
REF
ADDR[1:0]
SCL
SDA
AMI Semiconductor - Rev. 3.0
www.amis.com
FS7140
FS7145
Sync
Control
IPRG
Loop
Filter
Phase-
Frequency
Detector
UP
Charge
Pump
DOWN
Voltage
Controlled
Oscillator
Post
Divider
(N
Px
)
CMOS/PECL
Output
CLKP
CLKN
Feedback
Divider
(N
F
)
I
2
C
Interface
Registers
FS7140 / FS7145
Figure 2: Device Block Diagram
1
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 1: FS7140 Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
DI
DIO
DI
D
P
AI
AO
DI
D
P
AI
-
P
DI
U
-
P
DO
DO
Name
SCL
SDA
ADDR0
VSS
XIN
XOUT
ADDR1
VDD
IPRG
n/c
VSS
REF
n/c
VDD
CLKP
CLKN
Description
Serial Interface Clock (requires an external pull-up)
Serial Interface Data Input/Output (requires an external pull-up)
Address Select Bit "0"
Ground
Crystal Oscillator Feedback
Crystal Oscillator Drive
Address Select Bit "1"
Power Supply (+3.3V nominal)
PECL Current Drive Programming
No Connection
Ground
Reference Frequency Input
No Connection
Power Supply (+3.3V nominal)
Clock Output
Inverted Clock Output
Data Sheet
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output;
DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
Table 2: FS7145 Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
DI
DIO
DI
D
P
AI
AO
DI
D
P
AI
-
P
DI
U
DI
U
Name
SCL
SDA
ADDR0
VSS
XIN
XOUT
ADDR1
VDD
IPRG
n/c
VSS
REF
SYNC
VDD
CLKP
CLKN
Description
Serial Interface Clock (requires an external pull-up)
Serial Interface Data Input/Output (requires an external pull-up)
Address Select Bit "0"
Ground
Crystal Oscillator Feedback
Crystal Oscillator Drive
Address Select Bit "1"
Power Supply (+3.3V nominal)
PECL Current Drive Programming
No Connection
Ground
Reference Frequency Input
Synchronization Input
Power Supply (+3.3V nominal)
Clock Output
Inverted Clock Output
P
DO
DO
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output;
DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
AMI Semiconductor - Rev. 3.0
www.amis.com
2
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
4.0 Functional Block Description
4.1 Phase Locked Loop (PLL)
The phase locked loop is a standard phase- and frequency-
locked loop architecture. The PLL consists of a reference
divider, a phase-frequency detector (PFD), a charge pump, an
internal loop filter, a voltage-controlled oscillator (VCO), a
feedback divider, and a post divider.
The reference frequency (generated by either the on-board
crystal oscillator or an external frequency source), is first
reduced by the Reference Divider. The integer value that the
frequency is divided by is called the modulus and is denoted as
NR for the reference divider. This divided reference is then fed
into the PFD.
The VCO frequency is fed back to the PFD through the
feedback divider (the modulus is denoted by NF).
The PFD will drive the VCO up or down in frequency until the
divided reference frequency and the divided VCO frequency
appearing at the inputs of the PFD are equal. The input/output
relationship between the reference frequency and the VCO
frequency is then:
Data Sheet
modulus. Selected moduli below 12 are also permitted.
Moduli of: 4, 5, 8, 9, and 10 are also allowed (4 and 5 are not
available on date codes prior to 0108).
4.1.3 Post Divider
The post divider consists of three individually programmable
dividers, as shown in Figure 3.
POST1[3:0]
POST2[3:0]
POST3[1:0]
f
VCO
Post
Divider 1
(N
P1
)
Post
Divider 2
(N
P2
)
POST DIVIDER (N
Px
Post
Divider 3
(N
P3
)
)
f
CLK
Figure 3: Post Divider
The moduli of the individual dividers are denoted as N
P1
, N
P2
and N
P3
, and together they make up the array modulus N
Px
.
N
Px
=
N
P
1
´
N
P
2
´
N
P
3
The post divider performs several useful functions. First, it
allows the VCO to be operated in a narrower range of speeds
compared to the variety of output clock speeds that the device
is required to generate. Second, the extra integer in the
denominator permits more flexibility in the programming of the
loop for many applications where frequencies must be
achieved exactly.
Note that a nominal 50/50 duty factor is always preserved
(even for selections which have an odd modulus).
See Table 8 for additional information.
4.1.4 Crystal Oscillator
The FS7140 is equipped with a Pierce-type crystal oscillator.
The crystal is operated in parallel resonant mode. Internal
load capacitance is provided for the crystal. While a
recommended load capacitance for the crystal is specified,
crystals for other standard load capacitances may be used if
great precision of the reference frequency (100ppm or less) is
not required.
4.1.5 Reference Divider Source MUX
The source of frequency for the reference divider can be
chosen to be the device crystal oscillator or the REF pin by the
REFDSRC bit.
When not using the crystal oscillator, it is preferred to connect
f
VCO
f
=
REF
N
F
N
R
This basic PLL equation can be rewritten as
æ
N
f
VCO
=
f
REF
ç
F
ç
N
è
R
ö
÷
÷
ø
A post-divider (actually a series combination of three post
dividers) follows the PLL and the final equation for device
output frequency is:
f
CLK
æ
N
=
f
REF
ç
F
ç
N
è
R
öæ
1
֍
֍
N
øè
Px
ö
÷
÷
ø
4.1.1 Reference Divider
The reference divider is designed for low phase jitter. The
divider accepts the output of either the crystal oscillator circuit
or an external reference frequency. The reference divider is a
12 bit divider, and can be programmed for any modulus from 1
to 4095 (divide by 1 not available on date codes prior to 0108).
4.1.2 Feedback Divider
The feedback divider is based on a dual-modulus divider (also
called dual-modulus prescaler) technique. It permits division
by any integer value between 12 and 16383. Simply program
the FBKDIV register with the binary equivalent of the desired
AMI Semiconductor - Rev. 3.0
www.amis.com
3
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
X
IN
to V
SS
. Do not connect to X
OUT
.
When not using the REF input, it is preferred to leave it floating
or connected to V
DD
.
4.1.6 Feedback Divider Source MUX
The source of frequency for the feedback divider may be
selected to be either the output of the post divider or the output
of the VCO by the FBKDSRC bit.
Ordinarily, for frequency synthesis, the output of the VCO is
used. Use the output of the post divider only where a
deterministic phase relationship between the output clock and
reference clock are desired (line-locked mode, for example).
4.1.7 Device Shutdown
Two bits are provided to effect shutdown of the device if
desired, when it is not active. SHUT1 disables most externally
observable device functions.
SHUT2 reduces device
quiescent current to absolute minimum values. Normally, both
bits should be set or cleared together.
Serial communications capability is not disabled by either
SHUT1 or SHUT2.
Then:
R1 (from CLKP and CLKN output to VDD) =
R
LOAD
* V
DD
/ V
HI
=
75 * 3.3 / 2.4 =
103 ohms
R2 (from CLKP and CLKN output to GND) =
R
LOAD
* V
DD
/ (V
DD
- V
HI
) =
75 * 3.3 / (3.3 - 2.4) =
275 ohms
Rprgm (from VDD to IPRG pin) =
26 * (V
DD
* R
LOAD
) / (V
HI
- V
LO
) / 3 =
26 * (3.3 * 75) / (2.4 - 1.6) / 3 =
2.68 Kohms
Data Sheet
4.3 SYNC Circuitry
The FS7145 supports nearly instantaneous adjustment of the
output CLK phase by the SYNC input. Either edge direction of
SYNC (positive-going or negative-going) is supported.
Example (positive-going SYNC selected): Upon the negative
edge of SYNC input, a sequence begins to stop the CLK
output. Upon the positive edge, CLK resumes operation,
synchronized to the phase of the SYNC input (plus a
deterministic delay). This is performed by control of the device
post-divider. Phase resolution equal to ½ of the VCO period
can be achieved (approximately down to 2ns).
4.2 Differential Output Stage
The differential output stage supports both CMOS and pseudo-
ECL (PECL) signals. The desired output interface is chosen via
the programming registers.
If a PECL interface is used, the transmission line is usually
terminated using a Thévenin termination. The output stage can
only sink current in the PECL mode, and the amount of sink
current is set by a programming resistor on the LOCK/IPRG
pin. The ratio of output sink current to IPRG current is 13:1.
Source current for the CLKx pins is provided by the pull-up
resistors that are part of the Thévenin termination.
4.2.1 Example
Assume that it is desired to connect a PECL-type fanout buffer
right next to the FS7140.
Further assume:
· V
DD
= 3.3V
· desired V
HI
= 2.4V
· desired V
LO
= 1.6V
· equivalent R
LOAD
= 75 ohms
5.0 I
2
C-bus Control Interface
This device is a read/write slave device meeting all
Philips I
2
C-bus specifications except a "general
call." The bus has to be controlled by a master
device that generates the serial clock SCL,
controls bus access and generates the START
and STOP conditions while the device works as a slave. Both
master and slave can operate as a transmitter or receiver, but
the master device determines which mode is activated. A
device that sends data onto the bus is defined as the
transmitter, and a device receiving data as the receiver.
I
2
C-bus logic levels noted herein are based on a percentage of
the power supply (V
DD
). A logic-one corresponds to a nominal
voltage of V
DD
, while a logic-zero corresponds to ground (V
SS
).
AMI Semiconductor - Rev. 3.0
www.amis.com
4
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus is
not busy. During the data transfer, the data line (SDA) must
remain stable whenever the clock line (SCL) is high. Changes
in the data line while the clock line is high will be interpreted by
the device as a START or STOP condition. The following bus
conditions are defined by the I
2
C-bus protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
5.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL input is
high indicates a START condition. All commands to the device
must be preceded by a START condition.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held high
indicates a STOP condition. All commands to the device must
be followed by a STOP condition.
5.1.4 Data Valid
The state of the SDA line represents valid data if the SDA line
is stable for the duration of the high period of the SCL line after
a START condition occurs. The data on the SDA line must be
changed only during the low period of the SCL signal. There is
one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions is
determined by the master device, and can continue indefinitely.
However, data that is overwritten to the device after the first
eight bytes will overflow into the first register, then the second,
and so on, in a first-in, first-overwritten fashion.
5.1.5 Acknowledge
When addressed, the receiving device is required to generate
an acknowledge after each byte is received. The master device
must generate an extra clock pulse to coincide with the
acknowledge bit. The acknowledging device must pull the SDA
line low during the high period of the master acknowledge
clock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not
generating and acknowledge bit on the last byte that has been
read (clocked) out of the slave. In this case, the slave must
leave the SDA line high to enable the master to generate a
STOP condition.
Data Sheet
5.2 I
2
C-bus Operation
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital interface. The
crystal oscillator does not have to run for communication to
occur.
The device accepts the following I
2
C-bus commands:
5.2.1 Slave Address
After generating a START condition, the bus master broadcasts
a seven-bit slave address followed by a R/W bit. The address
of the device is:
A6
1
A5
0
A4
1
A3
1
A2
0
A1
X
A0
X
where X is controlled by the logic level at the ADDR pins. The
selectable ADDR bits allow four different FS7140 devices to
exist on the same bus. Note that every device on an I
2
C-bus
must have a unique address to avoid pos-sible bus conflicts.
5.2.2 Random Register Write Procedure
Random write operations allow the master to directly write to
any register. To initiate a write procedure, the R/W bit that is
transmitted after the seven-bit device address is a logic-low.
This indicates to the addressed slave device that a register
address will follow after the slave device acknowledges its
device address. The register address is written into the slave's
address pointer. Following an acknowledge by the slave, the
master is allowed to write eight bits of data into the addressed
register. A final acknowledge is returned by the device, and the
master generates a STOP condition.
If either a STOP or a repeated START condition occurs during
a register write, the data that has been transferred is ignored.
5.2.3 Random Register Read Procedure
Random read operations allow the master to directly read from
any register. To perform a read procedure, the R/W bit that is
transmitted after the seven-bit address is a logic-low, as in the
register write procedure. This indicates to the addressed slave
device that a register address will follow after the slave device
acknowledges its device address. The register address is then
written into the slave's address pointer.
Following an acknowledge by the slave, the master generates
a repeated START condition. The repeated START terminates
the write procedure, but not until after the slave's address
pointer is set. The slave address is then resent, with the R/W
bit set this time to a logic-high, indicating to the slave that data
will be read. The slave will acknowledge the device address,
and then transmits the eight-bit word. The master does not
AMI Semiconductor - Rev. 3.0
www.amis.com
5
嵌入式系统
