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FSTYC9055R3

64A, 60V, 0.023ohm, P-CHANNEL, Si, POWER, MOSFET, CERAMIC, LCC-3

器件类别:分立半导体    晶体管   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
零件包装代码
DLCC
包装说明
CHIP CARRIER, R-CBCC-N3
针数
3
Reach Compliance Code
not_compliant
ECCN代码
EAR99
外壳连接
DRAIN
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
60 V
最大漏极电流 (Abs) (ID)
64 A
最大漏极电流 (ID)
64 A
最大漏源导通电阻
0.023 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JESD-30 代码
R-CBCC-N3
JESD-609代码
e0
元件数量
1
端子数量
3
工作模式
ENHANCEMENT MODE
最高工作温度
150 °C
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装形状
RECTANGULAR
封装形式
CHIP CARRIER
极性/信道类型
P-CHANNEL
最大功率耗散 (Abs)
162 W
最大脉冲漏极电流 (IDM)
192 A
认证状态
Not Qualified
参考标准
MIL-S-19500
表面贴装
YES
端子面层
Tin/Lead (Sn/Pb)
端子形式
NO LEAD
端子位置
BOTTOM
晶体管应用
SWITCHING
晶体管元件材料
SILICON
Base Number Matches
1
文档预览
FSTYC9055D, FSTYC9055R
TM
Data Sheet
June 2000
File Number
4755.1
Radiation Hardened, SEGR Resistant
P-Channel Power MOSFETs
The Discrete Products Operation of Intersil has developed a
series of Radiation Hardened MOSFETs specifically
designed for commercial and military space applications.
Immunity to Single Event Effects (SEE) is combined with
100K RADs of total dose hardness to provide devices which
are ideally suited to harsh space environments. The dose
rate and neutron tolerance necessary for military
applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS)
structure. It is specially designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, motor drives,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.
Reliability screening is available as either commercial, TXV
equivalent of MIL-S-19500, or Space equivalent of
MIL-S-19500. Contact Intersil for any desired deviations
from the data sheet.
Formerly available as type TA17750T.
Features
• 64A, -60V, r
DS(ON)
= 0.023Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Typical SEE Immunity
- LET of 36MeV/mg/cm
2
with V
DS
up to 80% of Rated
Breakdown and V
GS
of 0V
- LET of 26MeV/mg/cm
2
with V
DS
up to 100% of Rated
Breakdown and V
GS
of 5V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 6nA Per-RAD (Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
2
- Usable to 3E14 Neutrons/cm
2
Symbol
D
G
S
Ordering Information
RAD LEVEL
10K
10K
100K
100K
100K
SCREENING LEVEL PART NUMBER/BRAND
Commercial
TXV
Commercial
TXV
Space
FSTYC9055D1
FSTYC9055D3
FSTYC9055R1
FSTYC9055R3
FSTYC9055R4
Packaging
SMD2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
©
Intersil Corporation 2000
FSTYC9055D, FSTYC9055R
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
FSTYC9055D, FSTYC9055R
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
-60
-60
64
41
192
±20
162
65
1.30
192
64
192
-55 to 150
300
UNITS
V
V
A
A
A
V
W
W
W/
o
C
A
A
A
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
-60
-
-2.0
-1.0
-
-
-
TYP
-
-
-
-
-
-
-
-
-
T
C
= 25
o
C
T
C
= 125
o
C
-
-
-
-
-
-
V
GS
= 0V to -20V
V
GS
= 0V to -12V
V
GS
= 0V to -2V
V
DD
= -30V,
I
D
= 64A
-
-
-
-
-
I
D
= 64A, V
DS
= -15V
V
DS
= -25V, V
GS
= 0V,
f = 1MHz
-
-
-
-
-
-
0.016
-
-
-
-
-
-
160
-
51
31
-7
7100
2130
370
-
MAX
-
-7.0
-6.0
-
25
250
100
200
-1.60
0.023
0.037
60
45
90
35
330
190
18
71
46
-
-
-
-
0.77
UNITS
V
V
V
V
µA
µA
nA
nA
V
ns
ns
ns
ns
nC
nC
nC
nC
nC
V
pF
pF
pF
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
I
GSS
V
DS(ON)
r
DS(ON)12
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
g(12)
Q
g(TH)
Q
gs
Q
gd
V
(PLATEAU)
C
ISS
C
OSS
C
RSS
R
θ
JC
V
DS
= -48V,
V
GS
= 0V
V
GS
=
±20V
V
GS
= -12V, I
D
= 64A
I
D
= 41A,
V
GS
= -12V
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate Charge at 12V
Threshold Gate Charge
Gate Charge Source
Gate Charge Drain
Plateau Voltage
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
V
DD
= -30V, I
D
= 64A,
R
L
= 0.47Ω, V
GS
= -12V,
R
GS
= 2.35Ω
2
FSTYC9055D, FSTYC9055R
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
V
SD
t
rr
TEST CONDITIONS
I
SD
= 64A
I
SD
= 64A, dI
SD
/dt = 100A/µs
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±20V,
V
DS
= 0V
V
GS
= 0, V
DS
= -48V
V
GS
= -12V, I
D
= 64A
V
GS
= -12V, I
D
= 41A
MIN
-60
-2.0
-
-
-
-
MAX
-
-6.0
100
25
-1.60
0.023
UNITS
V
V
nA
µA
V
MIN
-0.6
-
TYP
-
-
MAX
-1.8
120
UNITS
V
ns
Electrical Specifications up to 100K RAD
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= -12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
Single Event Effects (SEB, SEGR)
Note 4
ENVIRONMENT
(NOTE 5)
TEST
Single Event Effects Safe Operating Area
SYMBOL
SEESOA
ION
SPECIES
Ni
Br
Br
Br
NOTES:
4. Testing conducted at Brookhaven National Labs; witnessed by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm
2
(typical), T
C
= 25
o
C.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
TYPICAL LET
(MeV/mg/cm)
26
37
37
37
TYPICAL
RANGE (µ)
43
36
36
36
APPLIED
V
GS
BIAS
(V)
20
10
15
20
(NOTE 6)
MAXIMUM
V
DS
BIAS (V)
-60
-60
-36
-24
Performance Curves
Unless Otherwise Specified
LET = 26MeV/mg/cm
2
, RANGE = 43µ
LET = 37MeV/mg/cm
2
, RANGE = 36µ
-70
-60
-50
V
DS
(V)
-40
-30
-20
-10
0
0
5
10
V
GS
(V)
15
20
25
TEMP = 25
o
C
LIMITING INDUCTANCE (HENRY)
FLUENCE = 1E5 IONS/cm
2
(TYPICAL)
1E-3
1E-4
ILM = 10A
30A
1E-5
100A
300A
1E-6
1E-7
-10
-30
-100
DRAIN SUPPLY (V)
-300
-1000
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
3
FSTYC9055D, FSTYC9055R
Performance Curves
70
60
I
D
, DRAIN CURRENT (A)
50
I
D
, DRAIN (A)
40
30
20
10
0
-50
1
-1
100
100µs
Unless Otherwise Specified
(Continued)
500
T
C
= 25
o
C
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
-10
-100
V
DS
, DRAIN-TO-SOURCE VOLTAGE (V)
-200
0
50
100
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
PULSE DURATION = 250ms, V
GS
= -12V, I
D
= 41A
2.0
-12V
Q
G
NORMALIZED r
DS(ON)
1.5
Q
GS
V
G
Q
GD
1.0
0.5
CHARGE
0.0
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 5. BASIC GATE CHARGE WAVEFORM
10
FIGURE 6. NORMALIZED r
DS(ON)
vs JUNCTION TEMPERATURE
THERMAL RESPONSE (Z
θ
JC
)
1
0.5
0.2
0.1 0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
+ T
C
10
-3
10
-2
10
-1
P
DM
NORMALIZED
t
1
t
2
10
0
10
1
0.001
10
-5
10
-4
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
4
FSTYC9055D, FSTYC9055R
Performance Curves
Unless Otherwise Specified
500
I
AS
, AVALANCHE CURRENT (A)
(Continued)
100
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
10
0.1
1
t
AV
, TIME IN AVALANCHE (ms)
10
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
t
P
50W
V
GS
20V
t
AV
I
AS
50Ω
+
V
DD
-
50V-150V
BV
DSS
t
P
V
DS
V
DD
DUT
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
t
ON
V
DD
t
d(ON)
t
r
R
L
V
DS
0V
DUT
10%
V
DS
90%
t
OFF
t
d(OFF)
t
f
90%
10%
90%
V
GS
= -12V
R
GS
V
GS
10%
50%
PULSE WIDTH
50%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
5
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参数对比
与FSTYC9055R3相近的元器件有:FSTYC9055R1、FSTYC9055D1、FSTYC9055D3、FSTYC9055R4。描述及对比如下:
型号 FSTYC9055R3 FSTYC9055R1 FSTYC9055D1 FSTYC9055D3 FSTYC9055R4
描述 64A, 60V, 0.023ohm, P-CHANNEL, Si, POWER, MOSFET, CERAMIC, LCC-3 64A, 60V, 0.023ohm, P-CHANNEL, Si, POWER, MOSFET, CERAMIC, LCC-3 64A, 60V, 0.023ohm, P-CHANNEL, Si, POWER, MOSFET, CERAMIC, LCC-3 64A, 60V, 0.023ohm, P-CHANNEL, Si, POWER, MOSFET, CERAMIC, LCC-3 64A, 60V, 0.023ohm, P-CHANNEL, Si, POWER, MOSFET, CERAMIC, LCC-3
是否Rohs认证 不符合 不符合 不符合 不符合 不符合
零件包装代码 DLCC DLCC DLCC DLCC DLCC
包装说明 CHIP CARRIER, R-CBCC-N3 CHIP CARRIER, R-CBCC-N3 CHIP CARRIER, R-CBCC-N3 CHIP CARRIER, R-CBCC-N3 CHIP CARRIER, R-CBCC-N3
针数 3 3 3 3 3
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant _compli
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99
外壳连接 DRAIN DRAIN DRAIN DRAIN DRAIN
配置 SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压 60 V 60 V 60 V 60 V 60 V
最大漏极电流 (Abs) (ID) 64 A 64 A 64 A 64 A 64 A
最大漏极电流 (ID) 64 A 64 A 64 A 64 A 64 A
最大漏源导通电阻 0.023 Ω 0.023 Ω 0.023 Ω 0.023 Ω 0.023 Ω
FET 技术 METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 代码 R-CBCC-N3 R-CBCC-N3 R-CBCC-N3 R-CBCC-N3 R-CBCC-N3
JESD-609代码 e0 e0 e0 e0 e0
元件数量 1 1 1 1 1
端子数量 3 3 3 3 3
工作模式 ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
最高工作温度 150 °C 150 °C 150 °C 150 °C 150 °C
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER
极性/信道类型 P-CHANNEL P-CHANNEL P-CHANNEL P-CHANNEL P-CHANNEL
最大功率耗散 (Abs) 162 W 162 W 162 W 162 W 162 W
最大脉冲漏极电流 (IDM) 192 A 192 A 192 A 192 A 192 A
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
表面贴装 YES YES YES YES YES
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD
端子位置 BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
晶体管应用 SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING
晶体管元件材料 SILICON SILICON SILICON SILICON SILICON
参考标准 MIL-S-19500 - - MIL-S-19500 MIL-S-19500
厂商名称 - Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子)
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E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ
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