Fremont Micro Devices
FT25C32A DS
SPI Serial EEPROM
32K (8-bit wide)
FEATURES
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
FT25C32A V
CC
= 1.8V to 5.5V
Low voltage and low power operations
20MHz clock rate (5V)
Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively)
Partial page write operation allowed (32 bytes page write mode)
Self-timed programming cycle (5 ms max)
Block Write Protection (Protect 1/4, 1/2, or Entire Array)
Write protect pin for hardware data protection
High reliability: typically 1,000,000 cycles endurance
100 years data retention
Industrial temperature range (-40℃to 85℃)
Standard 8-pin DIP/SOP/TSSOP Pb-free packages
DESCRIPTION
The FT25C32A is 32768 bits of serial Electrical Erasable and Programmable Read Only Memory,
commonly known as EEPROM. They are organized as 4096 words of 8 bits (1 byte) each. The devices are
fabricated with proprietary advanced CMOS process for low power and low voltage applications. These
devices are available in standard 8-lead DIP, 8-lead SOP and 8-lead TSSOP packages. The memory is
accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The
HOLD
pin may be
used to suspend any serial communication without resetting the serial sequence. While the device is
paused, transitions on its inputs will be ignored. Our extended V
CC
range (1.8V to 5.5V) devices enables
wide spectrum of applications.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A - Page1
Fremont Micro Devices
FT25C32A DS
PIN CONFIGURATION
Pin Name
CS
Pin Function
Chip Select
Serial Clock Input
Serial Data Input
Serial Data Output
Pin Name
GND
VCC
WP
Pin Function
Ground
Power Supply
Write Protest
Suspends Serial Input
SCL
SI
SO
HOLD
All these packaging types come in conventional or Pb-free certified.
FT25C32A
SO
CS
1
2
3
4
GND
WP
8
VCC
7
HOLD
6
SCL
5
SI
8L DIP
8L SOP
8L TSSOP
Figure 1: Packaging Types
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature………………………………………………………………………-40
℃
to 85
℃
Storage temperature………………………………………………………………………………….-50
℃
to 125
℃
Input voltage on any pin relative to ground……………………………………………………-0.3V to V
CC
+ 0.3V
Maximum voltage……………………………………………………………………………………………………8V
ESD protection on all pins……………………………………………………………………………………>2000V
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to
the device. Functional operation of the device at conditions beyond those listed in the specification
is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or
functionality.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A-Page2
Fremont Micro Devices
FT25C32A DS
Block Diagram
VCC
GND
STATUS
REGISTER
MEMORY
ARRAY
ADDRESS
DECODER
DATA
REGISTER
SI
MODE
DECODE
LOGIC
OUTPUT
BUFFER
CS
WP
SCK
CLOCK
GENERATOR
SO
HOLD
Figure 2: Block Diagram
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A-Page3
Fremont Micro Devices
FT25C32A DS
PIN DESCRIPTIONS
(A) CHIP SELECT (
CS
)
The FT25C32A is selected when the
CS
pin is low. When the device is not selected, data will not be
accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
(B) Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
(C)Serial Output (SO)
The SO pin is used to transfer data out of the FT25C32A. During a read cycle, data is shifted out on this pin
after the falling edge of the serial clock.
(D) Serial Clock (SCK)
The SCK is used to synchronize the communication between a master and the FT25C32A. Instructions,
addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the
SO pin is updated after the falling edge of the clock input.
(E) Write Protect (
WP
)
This pin is used in conjunction with the WPEN bit in the status register to prohibit writes to the non-volatile
bits in the status register. When
WP
is low and WPEN is high, writing to the non-volatile bits in the status
register is disabled. All other operations function normally. When
WP
is high, all functions, including
writes to the non-volatile bits in the status register operate normally. If the WPEN bit is set,
WP
low during
a status register write sequence will disable writing to the status register. If an internal write cycle has
already begun,
WP
going low will have no effect on the write. The
WP
pin function is blocked when the
WPEN bit in the status register is low. This allows the user to install the FT25C32A in a system with
WP
pin grounded and still be able to write to the status register. The
WP
pin functions will be enabled when
the WPEN bit is set high.
(F) Hold (
HOLD
)
The
HOLD
pin is used in conjunction with the
CS
pin to select the FT25C32A. When the device is
selected and a serial sequence is underway,
HOLD
can be used to pause the serial communication with
the master device without resetting the serial sequence. To pause, the
HOLD
pin must be brought low
while the SCK pin is low. To resume serial communication, the
HOLD
pin is brought high while the SCK
pin is low (SCK may still toggle during
HOLD
). Inputs to the SI pin will be ignored while the SO pin is in the
high impedance state.
MEMORY ORGANIZATION
The FT25C32A devices have 128 pages respectively. Since each page has 32 bytes, random word
addressing to FT25C32A will require 12 bits data word addresses respectively.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A-Page4
Fremont Micro Devices
FT25C32A DS
DEVICE OPERATION
The FT25C32A utilizes an 8-bit instruction register. The list of instructions and their operation codes are
contained in Table A. All instructions, addresses, and data are transferred with the MSB first and start with a
high-to-low
CS
transition.
Table A Instruction Set for the FT25C32A
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
(A) STATUS REGISTER OPERATION
Table B Status Register Format
Bit 7
WPEN
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit2
BP0
Bit 1
WEN
Bit 0
RDY
WRITE ENABLE (WREN):
The device will power up in the write disable state when VCC is applied. All
programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI):
To protect the device against inadvertent writes, the Write Disable instruction
disables all programming modes. The WRDI instruction is independent of the status of the
WP
pin.
READ STATUS REGISTER (RDSR):
The Read Status Register instruction provides access to the status
register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR
instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits
are set by using the WRSR instruction.
Table C Status Register Bit Definition
Bit
Bit 0 (
RDY
)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bit 7 (WPEN)
Definition
Bit 0 = “0” (
RDY
) indicates the device is READY. Bit 0 = “1”
indicates the write cycle is in progress.
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1”
indicates the device is write enabled.
See table D.
See table D.
See table E.
Bits 4-6 are “0”s when device is not in an internal write cycle.
Bits 0-7 are “1” during an internal write cycle.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A-Page5
