128K x 8 Bit 5V EEPROM
FEATURES
•
Access Time: 120ns
•
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control Circuits
FT28C010-xxxxx-X
DESCRIPTION
The
Force FT28C010
is a 128K x 8 E
2
PROM, fabricated
with, high performance, floating gate
CMOS technology.
Like
most Force
programmable nonvolatile
memories
the
FT28C010
is a 5V only device. The
FT28C010
features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard
EPROMs.
The
FT28C010
supports a 256-byte page write operation,
effectively providing a 19
µs/byte
write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The
FT28C010
also features
DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the
FT28C010
supports Software Data
Protection option.
Force
E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
•
•
•
•
•
•
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 50mA
—Standby: 500
µ
A
Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
-X Manufactured using Xicor Die
FT28C010-xxxxx-AT
128K x 8 Bit 5V EEPROM
FEATURES
•
Fast Read Access Time 120ns
•
Automatic Page Write Operation
Internal Address and Data Latches for
128-Bytes Internal Control Timer
•
Fast Write Cycle Time
Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Operation
•
Low Power Dissipation
80 mA Active Current
300 µA CMOS Standby Current
•
Hardware and Software Data Protection
•
DATA Polling for End of Write Detection
•
High Reliability CMOS Technology
Endurance: 104
Data Retention: 10 Years
•
Single 5V
±
10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
-
AT Manufactured using Atmel Die
DESCRIPTION
The FT28C010 is a high-performance Electrically Erasable
and Programmable Read Only Memory. Its one megabit of
memory isorganised as 131,072 words by 8 bits.
Manufactured with advanced nonvolatile CMOS technology,
the device offersaccess times to 120 ns with power dissipa-
tion of just 440 mW. When the device isdeselected, the CMOS
standby current is less than 300 mA. (Cont)
Rev 1.3
1/31
March 2014
FT28C010-xxxxx-X
PIN CONFIGURATIONS
SIDE BRAZED/
CERDIP
FLAT PACK
SOIC (R)
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
I/O0
I/O1
A0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A1
13
A2
12
A4
10
8
A6
A12
A12
A15
A16
NC
VCC
WE
4 3 2
A14
A13
A8
A9
A11
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
1
32 31
A12
A15
A16
NC
VCC
WE
NC
PGA
I/O0
I/O2
I/O3
I/O5
I/O6
15
17
19
21
22
A0
14
A3
11
9
7
A5
A7
A15
A
4
CE
I/O1
VSS
I/O4
I/O7
16
18
20
23
24
A10
25
OE
26
A9
28
A13
30
A14
31
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
30
32 31 29
54 3 2
1
6
28
7
8
9
NC
30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
PLCC
LCC
EXTENDED LCC
I/O1
I/O2
VSS
A11
OE
CE
A10
I/O7
I/O6
I/O5
I/O4
I/O3
6
5
NC
2
NC
3
VCC
NC
36
34
NC
1
WE
35
NC
32
NC
33
TSOP
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
16
FT28C010
I/O2
VSS
FT28C010-xxxxx-AT
PIN CONFIGURATIONS
CERDIP, FLATPACK,SIDE
BRAZED
Top View
32 LCC
Top View
A12
A15
A16
NC
VCC
WE
NC
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
FT28C010
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
44LCC
Top View
A15
A16
NC
NC
NC
NC
VCC
WE
NC
NC
A14
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A0
I/O0
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
18
19
20
21
22
23
24
25
26
27
28
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
FT28C010
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
A12
A7
A6
A5
NC
NC
NC
A4
A3
A2
A1
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
FT28C010
39
38
37
36
35
34
33
32
31
30
29
A13
A8
A9
A11
NC
NC
NC
NC
OE
A10
CE
4
3
2
1
32
31
30
Rev 1.3
2/31
I/O3
I/O4
PGA
Top V iew
FT28C010
March 2014
I/O5
I/O6
7
FT28C010
26
(BOTTOM VIEW)
A8
29
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
FT28C010
A11
27
24
10
11
23
12
22
13
15 16 17 18 19 20 21
14
(TOP VIEW)
FT28C010
27
26
25
OE
A10
(TOP VIEW)
FT28C010
CE
I/O7
14 15 16 17 18 19 20
FT28C010-xxxxx-X
PIN DESCRIPTIONS
Addresses (A
0
–A
16
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the
FT28C010
through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
FT28C010.
FUNCTIONAL DIAGRAM
X BUFFERS
LATCHES AND
DECODER
1M-BIT
E2PROM
ARRAY
PIN NAMES
Symbol
A
0
–A
16
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
A8–A16
A0–A7
Y BUFFERS
LATCHES AND
DECODER
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
WE
VCC
VSS
CONTROL
LOGIC AND
TIMING
Rev 1.3
3/31
March 2014
FT28C010-xxxxx-X
DEVICE OPERATION
Read
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
Write
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The
FT28C010
supports both a
CE
and
WE
controlled write cycle. That is, the address
is latched by the falling edge of either
CE
or
WE,
which-
ever occurs last. Similarly, the data is latched internally by
the rising edge of either
CE
or
WE,
whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the
FT28C010
allows the entire
memory to be written in 5 seconds. Page write allows
two to two hundred fifty-six bytes of data to be consecu-
tively written to the
FT28C010
prior to the commence-
ment of the internal programming cycle. The host can
fetch data from another device within the system during
a page write operation (change the source address), but
the page address (A
8
through A
16
) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the
WE
HIGH to
LOW transition, must begin within 100
µs
of the falling
edge of the preceding
WE.
If a subsequent
WE
HIGH to
LOW transition is not detected within 100
µs,
the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The
FT28C010
provides the user two write operation
status bits. These can be used to optimise a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
DATA
Polling (I/O
7
)
The
FT28C010
features
DATA
Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed.
DATA
Polling allows a simple
bit test operation to determine the status of the
FT28C010,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O
7
(i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
7
will reflect true data. Note: If the
FT28C010
is in the protected state and an illegal write
operation is attempted
DATA
Polling will not operate.
Toggle Bit (I/O
6
)
The
FT28C010
also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle, I/O
6
will toggle from
HIGH to LOW and LOW to HIGH on subsequent at-
tempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
Rev 1.3
4/31
March 2014
FT28C010-xxxxx-X
DATA
Polling I/O
7
Figure 2.
DATA
Polling Bus Sequence
WE
LAST
WRITE
CE
OE
VIH
VOH
VOL
An
An
An
An
An
An
An
FT28C010
READY
I/O7
HIGH Z
A0–A14
Figure 3.
DATA
Polling Software Flow
DATA
Polling can effectively halve the time for writing to
the
FT28C010.
The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3 illustrates one method of implement-
ing the routine.
NO
WRITE DATA
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
I/O7
COMPARE?
YES
FT28C010
READY
NO
Rev 1.3
5/31
March 2014
