Intel
®
100 Series and Intel
®
C230
Series Chipset Family Platform
Controller Hub (PCH)
Datasheet – Volume 1 of 2
May 2016
Document Number: 332690-004EN
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2
Datasheet, Volume 1
Contents
1
Introduction
............................................................................................................ 19
1.1
About this Manual ............................................................................................. 19
1.2
References ....................................................................................................... 19
1.3
Overview ......................................................................................................... 19
1.4
PCH SKUs ........................................................................................................ 21
PCH Controller Device IDs
....................................................................................... 25
2.1
Device and Revision ID Table .............................................................................. 25
Flexible I/O
............................................................................................................. 27
3.1
Acronyms......................................................................................................... 27
3.2
References ....................................................................................................... 27
3.3
Overview ......................................................................................................... 27
3.4
Description ....................................................................................................... 27
3.4.1 PCH-H Flexible I/O ................................................................................. 28
3.5
HSIO Port Selection ........................................................................................... 29
3.5.1 PCIe/SATA Port Selection ........................................................................ 29
Memory Mapping
..................................................................................................... 31
4.1
Overview ......................................................................................................... 31
4.2
Functional Description........................................................................................ 31
4.2.1 PCI Devices and Functions....................................................................... 31
4.2.2 Fixed I/O Address Ranges ....................................................................... 32
4.2.3 Variable I/O Decode Ranges .................................................................... 34
4.3
Memory Map..................................................................................................... 35
4.3.1 Boot Block Update Scheme ...................................................................... 37
System Management
............................................................................................... 39
5.1
Acronyms......................................................................................................... 39
5.2
References ....................................................................................................... 39
5.3
Overview ......................................................................................................... 39
5.4
Features .......................................................................................................... 39
5.4.1 Theory of Operation................................................................................ 40
5.4.1.1 Detecting a System Lockup ........................................................ 40
5.4.1.2 Handling an Intruder ................................................................. 40
5.4.1.3 Detecting Improper Flash Programming ....................................... 40
5.4.2 TCO Modes ............................................................................................ 41
5.4.2.1 TCO Compatible Mode ............................................................... 41
5.4.2.2 Advanced TCO Mode ................................................................. 42
High Precision Event Timer (HPET)
.......................................................................... 43
6.1
References ....................................................................................................... 43
6.2
Overview ......................................................................................................... 43
6.2.1 Timer Accuracy ...................................................................................... 43
6.2.2 Timer Off-load ....................................................................................... 43
6.2.3 Off-loadable Timer.................................................................................. 44
6.2.4 Interrupt Mapping .................................................................................. 45
6.2.4.1 Mapping Option #1 (Legacy Replacement Option) ......................... 45
6.2.4.2 Mapping Option #2 (Standard Option) ......................................... 45
6.2.4.3 Mapping Option #3 (Processor Message Option)............................ 45
6.2.5 Periodic Versus Non-Periodic Modes .......................................................... 46
6.2.5.1 Non-Periodic Mode .................................................................... 46
6.2.5.2 Periodic Mode ........................................................................... 46
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6.2.6
6.2.7
6.2.8
6.2.9
7
Enabling the Timers ................................................................................46
Interrupt Levels......................................................................................47
Handling Interrupts.................................................................................47
Issues Related to 64-Bit Timers with 32-Bit Processors ................................47
Thermal Management
..............................................................................................49
7.1
PCH Thermal Sensor ..........................................................................................49
7.1.1 Modes of Operation .................................................................................49
7.1.2 Temperature Trip Point............................................................................49
7.1.3 Thermal Sensor Accuracy (Taccuracy) .......................................................49
7.1.4 Thermal Reporting to an EC .....................................................................49
7.1.5 Thermal Trip Signal (PCHHOT#) ...............................................................50
Power and Ground Signals
.......................................................................................51
Pin Straps
................................................................................................................53
Electrical Characteristics..........................................................................................57
10.1 Absolute Maximum Ratings .................................................................................57
10.2 Thermal Specification .........................................................................................57
10.3 PCH Power Supply Range....................................................................................58
10.4 General DC Characteristics..................................................................................58
10.5 AC Characteristics..............................................................................................69
10.5.1 Panel Power Sequencing and Backlight Control ...........................................71
10.6 Overshoot/Undershoot Guidelines ........................................................................89
Ballout Definition
.....................................................................................................91
8254 Timers...........................................................................................................
103
12.1 Overview ........................................................................................................ 103
12.1.1 Timer Programming .............................................................................. 103
12.1.2 Reading from the Interval Timer ............................................................. 104
12.1.2.1 Simple Read ........................................................................... 104
12.1.2.2 Counter Latch Command .......................................................... 105
12.1.2.3 Read Back Command ............................................................... 105
Integrated High Definition Audio
........................................................................... 107
13.1 Acronyms ....................................................................................................... 107
13.2 References...................................................................................................... 107
13.3 Overview ........................................................................................................ 107
13.4 Signal Description ............................................................................................ 107
13.5 Integrated Pull-Ups and Pull-Downs.................................................................... 108
13.6 I/O Signal Planes and States ............................................................................. 109
13.7 Features ......................................................................................................... 109
13.7.1 High Definition Audio Controller Capabilities ............................................. 109
13.7.2 Audio DSP Capabilities........................................................................... 110
13.7.3 High Definition Audio Link Capabilities ..................................................... 110
13.7.4 Display Audio Link Capabilities................................................................ 110
13.7.5 DSP I/O Peripherals Capabilities.............................................................. 110
Controller Link
....................................................................................................... 111
14.1 Overview ........................................................................................................ 111
14.2 Signal Description ............................................................................................ 111
14.3 Integrated Pull-Ups and Pull-Downs.................................................................... 111
14.4 I/O Signal Planes and States ............................................................................. 111
14.5 Functional Description ......................................................................................111
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Processor Sideband Signals
................................................................................... 113
15.1 Acronyms....................................................................................................... 113
15.2 Overview ....................................................................................................... 113
15.3 Signal Description ........................................................................................... 113
15.4 Integrated Pull-Ups and Pull-Downs ................................................................... 113
15.5 I/O Signal Planes and States............................................................................. 113
15.6 Functional Description...................................................................................... 114
Digital Display Signals
........................................................................................... 115
16.1 Acronyms....................................................................................................... 115
16.2 References ..................................................................................................... 115
16.3 Signal Description ........................................................................................... 115
16.4 Embedded DisplayPort* (eDP*) Backlight Control Signals ..................................... 116
16.5 Integrated Pull-Ups and Pull-Downs ................................................................... 116
16.6 I/O Signal Planes and States............................................................................. 116
Enhanced Serial Peripheral Interface (eSPI)
......................................................... 119
17.1 Acronyms....................................................................................................... 119
17.2 References ..................................................................................................... 119
17.3 Overview ....................................................................................................... 119
17.4 Signal Description ........................................................................................... 119
17.5 Integrated Pull-Ups and Pull-Downs ................................................................... 120
17.6 I/O Signal Planes and States............................................................................. 120
17.7 Functional Description...................................................................................... 120
17.7.1 Features ............................................................................................. 120
17.7.2 Protocols ............................................................................................. 121
17.7.3 WAIT States from eSPI Slave ................................................................. 122
17.7.4 In-Band Link Reset ............................................................................... 122
17.7.5 Slave Discovery ................................................................................... 122
17.7.6 Channels and Supported Transactions ..................................................... 122
17.7.6.1 Peripheral Channel (Channel 0) Overview................................... 122
17.7.6.2 Virtual Wire Channel (Channel 1) Overview ................................ 123
17.7.6.3 Out-of-Band Channel (Channel 2) Overview ............................... 124
17.7.6.4 Flash Access Channel (Channel 3) Overview ............................... 126
General Purpose Input and Output (GPIO)
............................................................ 129
18.1 Acronyms....................................................................................................... 129
18.2 References ..................................................................................................... 129
18.3 Overview ....................................................................................................... 129
18.4 Signal Description ........................................................................................... 130
18.5 Integrated Pull-ups and Pull-downs.................................................................... 141
18.6 Functional Description...................................................................................... 141
18.6.1 SMI# / SCI and NMI ............................................................................. 141
18.6.2 Blink/PWM Capability ............................................................................ 141
18.6.2.1 PWM Programing Sequence ...................................................... 142
18.6.3 Triggering ........................................................................................... 143
18.6.4 Sx GPIO Implementation Considerations ................................................. 143
18.6.5 GPIO Ownership................................................................................... 144
18.6.6 GPIO Pad Voltage Tolerance Configuration ............................................... 144
Intel
®
Serial I/O Generic SPI (GSPI) Controllers...................................................
145
19.1 Acronyms....................................................................................................... 145
19.2 References ..................................................................................................... 145
19.3 Overview ....................................................................................................... 145
19.4 Signal Description ........................................................................................... 145
19.5 Integrated Pull-Ups and Pull-Downs ................................................................... 146
19.6 I/O Signal Planes and States............................................................................. 146
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