GS8160Z18/36T-250/225/200/166/150/133
Commercial Temp
Industrial Temp
Features
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8160Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8160Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Functional Description
The GS8160Z18/36T is an 18Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
Parameter Synopsis
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow
Through
2-1-1-1
3.3 V
2.5 V
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Curr
(x18)
Curr
(x32/x36)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
280
330
275
320
5.5
5.5
175
200
175
200
255
300
250
295
6.0
6.0
165
190
165
190
230
270
230
265
6.5
6.5
160
180
160
180
200
230
195
225
7.0
7.0
150
170
150
170
185
215
180
210
7.5
7.5
145
165
145
165
165
190
165
185
8.5
8.5
135
150
135
150
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
Rev: 2.17 11/2004
1/24
© 1998, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
GS8160Z18T Pinout
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
FT
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
A
E
1
E
2
NC
NC
B
B
B
A
E
3
V
DD
V
SS
CK
W
CKE
G
ADV
A
A
A
A
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
Rev: 2.17 11/2004
LBO
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
2/24
© 1998, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
GS8160Z36T Pinout
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
FT
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
W
CKE
G
ADV
A
A
A
A
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
Rev: 2.17 11/2004
LBO
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
3/24
© 1998, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A
DQ
B
DQ
C
DQ
D
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
—
I/O
I/O
I/O
I/O
In
In
In
In
In
In
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
Core power supply
Ground
Output driver power supply
Rev: 2.17 11/2004
4/24
© 1998, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
GS8160Z18/36 NBT SRAM Functional Block Diagram
DQa
–
DQn
FT
Q
Write Data
K
Register 1
D
Write Data
Write Address
Burst
Counter
K
Register 2
SA1’
SA0’
Read, Write and
Data Coherency
D
K
K
Control Logic
SA1
SA0
K
Write Address
Register 1
Match
Q
B
C
LBO
B
D
W
B
A
B
B
K
FT
E
1
E
2
ADV
E
3
CK
Rev: 2.17 11/2004
A
0
–An
5/24
© 1998, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CKE
G
Write Drivers
Memory
Array
Register 2
K
Sense Amps
K