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GS8672T19/37BE-450/400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• On-Chip ECC with virtually zero SER

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with 18Mb, 36Mb and 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaDDR-II+

Burst of 2 ECCRAM

Clocking and Addressing Schemes

450 MHz–300 MHz

1.8 V V

1.5 V I/O

The GS8672T19/37BE SigmaDDR-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaDDR-II+ B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaDDR-II+ B2 ECCRAM is always one address

pin less than the advertised index depth (e.g., the 4M x 18 has

an 2M addressable index).

SigmaDDR™ ECCRAM Overview

The GS8672T19/37BE ECCRAMs are built in compliance

with the SigmaDDR-II+ SRAM pinout standard for Common

I/O synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672T19/37BE SigmaCIO ECCRAMs are

just one element in a family of low power, low voltage HSTL

I/O ECCRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the

Byte

Write Contol

section for further information.

Parameter Synopsis

-450

tKHKH

tKHQV

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

-375

2.66 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.02a 8/2017

1/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T19/37BE-450/400/375/333/300

2M x 36 SigmaDDR-II+ ECCRAM—Top View

Doff

TDO

(144Mb)

DQ27

DQ29

DQ30

DQ31

REF

DQ33

DQ35

TCK

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

DDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

R/W

DDQ

BW2

BW3

QVLD

MCL

BW1

BW0

DDQ

DQ17

DQ15

REF

DQ13

DQ12

DQ11

DQ9

TMS

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

11 x 15 Bump BGA—13 x 15 mm

Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to

DQ27:DQ35

2. MCL = Must Connect Low

Rev: 1.02a 8/2017

2/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T19/37BE-450/400/375/333/300

4M x 18 SigmaDDR-II+ ECCRAM—Top View

Doff

TDO

DQ9

DQ12

REF

DQ15

TCK

DQ10

DQ11

DQ13

DDQ

DQ14

DQ16

DQ17

R/W

DDQ

BW1

QVLD

MCL

BW0

DDQ

DQ7

REF

DQ4

DQ1

TMS

DQ8

DQ6

DQ5

DQ3

DQ2

DQ0

TDI

11 x 15 Bump BGA—13 x 15 mm

Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17

2. MCL = Must Connect Low

Rev: 1.02a 8/2017

3/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T19/37BE-450/400/375/333/300

Pin Description Table

Symbol

R/W

BW0–BW3

TMS

TDI

TCK

TDO

REF

MCL

Description

Synchronous Address Inputs

Synchronous Read/Write

Synchronous Byte Writes

Synchronous Load Pin

Input Clock

Test Mode Select

Test Data Input

Test Clock Input

Test Data Output

HSTL Input Reference Voltage

Output Impedance Matching Input

Must Connect Low

Data I/O

Disable DLL when low

Output Echo Clock

Power Supply

Isolated Output Buffer Supply

Power Supply: Ground

Q Valid Output

No Connect

No Function

Type

Input

Output

Input

—

Input/Output

Input

Output

Supply

Output

—

Comments

—

Active Low

x18/x36 only

Active Low

Active High

Active Low

—

Three State

Active Low

—

1.8 V Nominal

1.5 V Nominal

—

Doff

DDQ

QVLD

Notes:

1. NC = Not Connected to die or any other pin

2. NF = No Function. There is an electrical connection to this input pin, but the signal has no function in the device. It can be left unconnected,

or tied to V

or V

DDQ.

3. K, or K cannot be set to V

REF

voltage.

Rev: 1.02a 8/2017

4/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T19/37BE-450/400/375/333/300

Background

Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaDDR-II+ ECCRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs

are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed

Common I/O SRAMs data bandwidth in half.

Burst Operations

Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will

respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in

the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,

if intervening deselect cycles are inserted.

Deselect Cycles

Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to

the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer

and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from

loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer

operations.

SigmaDDR-II+ B2 ECCRAM Read Cycles

The ECCRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The

read command (LD low and R/W high) is clocked into the ECCRAM by a rising edge of K.

SigmaDDR-II+ B2 ECCRAM Write Cycles

The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The ECCRAM executes "late write" data

transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write

command (LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the

ECCRAM captures data in on the next rising edge of K, for a total of two transfers per address load.

Rev: 1.02a 8/2017

5/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.