FICATION ADDENDUM, Serial Synchronous Interface SSI):
ut provides effective synchronization in a closed-loop control system. A clock
ain from a controller is used to shift out sensor data: one bit of position data is
ted to the controller per clock pulse received by the sensor. The use of a
LTR
ial driver permits reliable transmission of data over long distances in
ments that may be electrically noisy. The encoder utilizes a clock signal,
ECO_500
A
d by the user interface, to time the data transmission. Receiving electronics must
an appropriate receiver as well as line terminating resistors. An optional parity
ailable to validate the transmitted data.
SSI output provides effective synchronization in a closed-loop control system. A clock pulse train from a controller is used to clock out sensor data:
H25D - Square Flange
0.3747
Cable impedance creates a transmission delay, shifting the phase relationship between the clock pulse and the data. If this pulse shift exceeds 180 , then the wrong bit position will be sampled
Ø
0.3745
by the receiver.
by the sensor. The use of a
is a function of the cable
The
frequency, therefore,
one bit of position data is transmitted to the controller per one clock pulse received
AWG,maximum3allowable clock part number 37048-003
differential
group
permits reliable
driver
MS STYLE 1.30 (SM 14/19)
EM CONNECTOR
REVISIONS
length. For 24
stranded, pair cable (BEI
or equivalent) the
CONNECTOR
Ø 1.2500
0.300
POSITION
1.2495
delay is
noisy. The encoder utilizes a clock signal, provided by the user inter-
below shows the
0.100
transmission of data over long
DESCRIPTION
in environments that may be electrically
1.36nS/ft. The tablephase shift of less maximum transmission rate allowable as a function
distances
DATE
APPR
SM CONNECTOR
of cable length to ensure a
than 90 .
.100 MIN
POSITION
4/13/05
2.064 TYP
MS STYLE 1.30 (SM 14/19)
face, to time the data transmission. Receiving electronics must include an appropriate
(KHz) = 92,000/Cable Length (ft)
as line terminating resistors.
receiver as well
EM CONNECTOR
CLOCK: Maximum
1.032
CONNECTOR
0.88 ± 0.03
0.12
0.125
0.21 R
Ø 2.500
Features :
•
Synchronous transmission
•
Transmission lengths to 1000 feet
•
Accepts clock rates from 100 KHz to 1.8 MHz
onous transmission
485 compatible
mission lengths to 1000 feet
s clock rates from 100 KHz to 1.8 MHz
bit option is available
Ø 2.500
Ø 2.52
0.30
MAX
Cable impedance can create a transmission delay, in effect, shifting the
Ø 2.275
1.2500
phase relationship between the clock pulse and the data. If this phase shift
2.50
Ø 1.2495
1. Output driver of the encoder is a MAX 491 transceiver in transmit mode. The
0.88 ± 0.03
0.3747
Ø 0.218 4 HOLES
Ø
1.38
0.3745
exceeds 180°, then the wrong bit position will be sampled by the receiver.
(Ø 2.919 B.C. REF)
recommended receiver is a MAX 491 transceiver in receive mode.
0.255
Ø 2.52
Ø 1.2500
0.30
1.2495
As a result, the maximum allowable clock frequency is a function
MAX
the
of
SSI Compatible Serial Code (S3):
2. Controller provides a series of pulses (or differential pulse pairs) on
2.064
cable length. For 24 AWG, stranded, 3 pair cable (BEI part number 37048-
30°
Transmission
Ø 2.275
0.21 R
H25E -
1.032 TYP
Servo Mount
2.50
the CLOCK input lines.
nce:
MS STYLE 1.30 (SM 14/19)
003 or equivalent) the group delay is 1.36ns/ft. The table below shows
EM CONNECTOR
0.88 ± 0.03
0.3747
Ø
CONNECTOR
3. On the first HIGH-to-LOW CLOCK transition, the encoder latches its data
1.38
0.300
POSITION
0.3745
from the encoder is sent with a MAX 491 transceiver in transmit mode. It is
0.125
the maximum transmission rate allowable as a function of cable
SM CONNECTOR
length to
0.100
mended to use any RS-422/485 compatible receiver and provide a termination resistor
2.650
at the
your specific voltage and DATA line length.
current position and prepares to transmit.
1.2500.100 MIN
0.125
Ø
on the RS-422/485 specification for
POSITION
SQUARE
1.2495
ensure a phase shift of less than 90°.
0.34
MS STYLE 1.30 (SM 14/19)
LOCK signals are RS-422/485 compatible, differential TTL, with 180 Ohm termination
EM CONNECTOR
F4
ors internal to the encoder.
4. Controller reads data on the falling edge of the next 15 clock cycles.
A series of pulses from the controller, on the CLOCK
CONNECTOR
Ø 2.500
0.300
POSITION
6-32 UNC-2B
advances the data.
2.064
0.100
TYP
0.125
30°
0.250 Min. Deep
2.500
Ø 2.498
e first HIGH-to-LOW CLOCK transition, the encoder latches
a
data at the current
and is always HIGH.
SM CONNECTOR
0.21 R
5. The first bit is
its
START bit
1.032
3 places equally spaced
0.125
on and prepares to transmit. The DATA signal during this transition is a START bit,
Ø 0.218 4 HOLES
1.2500
on a Ø 2.00 bolt circle.
CLOCK, Maximum (kHz) = 92,000 / Cable Length
used with a standard cable/connector assembly,
.100 MIN
(ft)CW
POSITION
2.50
Ø 1.2495
(Ø 2.919 B.C. REF)
is always HIGH.
*Connector is a
an MS3106F18-1S
BEI P/N: 924-31186-18XX.
6. Next comes 13 data bits beginning with the most significant bit (MSB)
MS3102E18-1P, 10-pin connector on the encoder body and mates tocable length in feet,connector or can be
ncoder shifts data to the DATA line on each LOW-to-HIGH clock transition, beginning
Ø 2.625
= 10 feet)
Ø 2.500
he MSB. The controller reads data on the HIGH-to-LOW transiton of the next 12 clock
Cable Length (ft)
50
(XX =
100
Ø
200
ie. 10
300 500 1000
0.255
2.500
and ending with the parity bit.
ending with the LSB. The parity bit (if parity option is specified) is clocked out on
On 12 bit encoders, bit 13 is LOW. When
2.52
Ø 2.498
0.30
supply voltage. To reverse the count direction,
th clock cycle. When the parity option is used, the 13th bit output is a logic LOW on
Direction Control: Standard is CW for increasing count when viewed from the shaft end. Direction Control (Pin C) is normally HIGH (or N/C) and is pulled up internally to the positive
2.650
MAX
1.2500
2.50
it Encoder or the LSB of a 13 bit Encoder.
not ordered, parity is LOW.
parity is
SQUARE
Ø 1.2495
Max Freq (kHz)
1800
Pin C must be pulled to LO (0V)
200 100
900 500 300
0.34
is even. The sum of all data bits and the parity bit is even.
Ø 2.275
Ø
SEAL
the last CLOCK LOW-to-HIGH transition, a minimum of 30 microseconds must pass
NOTE:
SHAFT
2.625
NOT
F4
7. After
e the beginning of the next CLOCK series.
the last CLOCK HIGH-to-LOW transition, a minimum of 40 micro-
0.255
AVAILABLE ON H25 G
Ø 2.52
6-32 UNC-2B
0.3747
0.30
0.88 ± 0.03
Ø
SSI Compatible Output with Parity Option Timing Diagram:
0.3745
1.38
0.250 Min. Deep
MAX
seconds must pass before the beginning of the next CLOCK series.
