H5PS5162GFR Series
512Mb DDR2 SDRAM
H5PS5182GFR-xxC
H5PS5182GFR-xxI
H5PS5182GFR-xxL
H5PS5182GFR-xxJ
H5PS5162GFR-xxC
H5PS5162GFR-xxI
H5PS5162GFR-xxL
H5PS5162GFR-xxJ
This document is a general product description and is subject to change without notice. SK hynix Inc. does not assume any responsi-
bility for use of circuits described. No patent licenses are implied.
Rev. 1.7 / Feb. 2013
1
H5PS5162GFR series
Revision History
Rev.
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
History
Release
Updated IDD Specification
Added IDD6 Low Power Products
Corrected typo
Corrected typo
Merged with x8 series(H5PS5182GFR)
Corrected typo
New revised logo
Draft Date
Sep. 2010
Sep.2010
Nov.2010
Dec.2010
Feb.2011
Mar.2011
Sep.2011
Feb. 2013
Rev.1.7 / Feb. 2013
2
H5PS5162GFR series
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Features
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev.1.7 / Feb. 2013
3
H5PS5162GFR series
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD ,VDDQ =1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 2, 3, 4, 5, 6 and 7 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4 / 8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 84ball FBGA(x16) : 7.5mm x 12.5mm
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Self-Refresh High Temperature Entry
• Partial Array Self Refresh support
Rev.1.7 / Feb. 2013
4
H5PS5162GFR series
Ordering Information
Part No.
H5PS5182GFR-xx*C
H5PS5182GFR-xx*I
H5PS5182GFR-xx*L
64Mx8
Configura-
tion
Power Consumption
Normal Consumption
Normal Consumption
Low Power Consumption
(IDD6 Only)
Low Power Consumption
(IDD6 Only)
Normal Consumption
Normal Consumption
32Mx16
Low Power Consumption
(IDD6 Only)
Low Power Consumption
(IDD6 Only)
Operation Temp
Commercial
Industrial
Commercial
60 Ball
fBGA
Package
H5PS5182GFR-xx*J
H5PS5162GFR-xx*C
H5PS5162GFR-xx*I
H5PS5162GFR-xx*L
Industrial
Commercial
Industrial
Commercial
84 Ball
fBGA
H5PS5162GFR-xx*J
Note:
Industrial
-XX* is the speed bin, refer to the Operating Frequency table for complete part number.
-
SK hynix Inc. Halogen-free products are compliant to RoHS.
SK hynix Inc. supports Lead & Halogen free parts for each speed grade with same specification, except Lead free
materials.
We'll add "R" character after "F" for Lead & Halogen free products
Rev.1.7 / Feb. 2013
5
瑞萨电子MCU
