ADE-XXX-XXX
HM628128A Series
131,072-word
×
8-bit High Speed CMOS Static RAM
Rev. X
January 1995
The Hitachi HM628128A is a CMOS static RAM
organized 128 kword
×
8 bit. It realizes higher
density, higher performance and low power
consumption by employing 0.8 µm Hi-CMOS
process technology.
It offers low power standby power dissipation;
therefore, it is suitable for battery back-up systems.
The device, packaged in a 525-mil SOP (460-mil
body SOP) or a 600-mil plastic DIP, or a 8
×
20
mm TSOP with thickness of 1.2 mm, is available
for high density mounting. TSOP package is
suitable for cards, and reverse type TSOP is also
provided.
Features
• High speed
— Fast access time: 55/70/85/100 ns (max)
• Low power
— Active: 75 mW (typ)
— Standby: 10 µW (typ)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Capability of battery back up operation
2 chip selection for battery back up
HM628128A Series
Ordering Information
Type No.
HM628128ALP–5
HM628128ALP–7
HM628128ALP–8
HM628128ALP–10
HM628128ALP–5L
HM628128ALP–7L
HM628128ALP–8L
HM628128ALP–10L
HM628128ALP–5SL
HM628128ALP–7SL
HM628128ALP–8SL
HM628128ALP–10SL
HM628128ALFP–5
HM628128ALFP–7
HM628128ALFP–8
HM628128ALFP–10
HM628128ALFP–5L
HM628128ALFP–7L
HM628128ALFP–8L
HM628128ALFP–10L
Access
time
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
525-mil 32-pin
plastic SOP
(FP-32D)
Package
600-mil 32-pin
plastic DIP
(DP-32)
Type No.
HM628128ALT–5
HM628128ALT–7
HM628128ALT–8
HM628128ALT–10
HM628128ALT–5L
HM628128ALT–7L
HM628128ALT–8L
HM628128ALT–10L
HM628128ALT-5SL
HM628128ALT-7SL
HM628128ALT-8SL
HM628128ALT-10SL
HM628128ALR–5
HM628128ALR–7
HM628128ALR–8
HM628128ALR–10
HM628128ALR–5L
HM628128ALR–7L
HM628128ALR–8L
HM628128ALR–10L
HM628128ALR-5SL
HM628128ALR-7SL
HM628128ALR-8SL
HM628128ALR-10SL
Access
time
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
100 ns
8 mm
×
20 mm
32-pin TSOP
(reverse type)
(TFP-32DR)
Package
8 mm
×
20 mm
32-pin TSOP
(normal type)
(TFP-32D)
HM628128ALFP–5SL 55 ns
HM628128ALFP–7SL 70 ns
HM628128ALFP–8SL 85 ns
HM628128ALFP–10SL 100 ns
2
HM628128A Series
Pin Arrangement
HM628128ALP/ALFP Series
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
HM628128ALR Series
A11
A9
A8
A13
WE
CS2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A3
HM628128ALT Series
A4
A5
A6
A7
A12
A14
A16
NC
V
CC
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Top View)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CS1
A10
OE
Pin Description
Pin name
A0 – A16
I/O0 – I/O7
CS1
CS2
WE
Function
Address
Input/output
Chip select 1
Chip select 2
Write enable
Pin name
OE
NC
V
CC
V
SS
Function
Output enable
No connection
Power supply
Ground
3
HM628128A Series
Block Diagram
(MSB)
A13
A15
A6
A7
A12
A14
A16
A5
A4
(LSB)
Row
Decoder
•
•
•
•
•
V
CC
V
SS
Memory Matrix
512 x 2,048
I/O0
Input
Data
Control
I/O7
•
•
Column I/O
Column Decoder
•
•
(LSB)
A8 A9 A11 A10 A0 A1 A2 A3
•
•
(MSB)
CS2
CS1
WE
OE
Timing Pulse Generator
Read/Write Control
Function Table
CS1
H
X
L
L
L
L
Note:
CS2
X
L
H
H
H
H
X: H or L
OE
X
X
H
L
H
L
WE
X
X
H
H
L
L
Mode
Standby
Standby
Output disable
Read
Write
Write
V
CC
current
I
SB
, I
SB1
I
SB
, I
SB1
I
CC
I
CC
I
CC
I
CC
I/O pin
High-Z
High-Z
High-Z
Dout
Din
Din
Ref. cycle
—
—
—
Read cycle
Write cycle (1)
Write cycle (2)
4
HM628128A Series
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Voltage on any pin relative to V
SS*1
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Note:
Symbol
V
CC
V
T
P
T
Topr
Tstg
Tbias
Value
–0.5 to +7.0
–0.5
*2
to V
CC
+ 0.3
*3
1.0
0 to +70
–55 to +125
–10 to +85
Unit
V
V
W
°C
°C
°C
1. With respect to V
SS
2. –3.0 V for pulse half-width
≤
30 ns
3. Maximum voltage is 7.0V.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input voltage
(HM628128A-7/8/10)
Input voltage
(HM628128A-5)
Note:
V
IH
V
IL
V
IH
V
IL
Min
4.5
0
2.2
–0.3
*1
2.4
–0.3
*1
Typ
5.0
0
—
—
—
—
Max
5.5
0
V
CC
+ 0.3
0.8
V
CC
+ 0.3
0.8
Unit
V
V
V
V
V
V
1. –3.0 V for pulse half-width
≤
30 ns
5
